Issued Patents All Time
Showing 1–25 of 192 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432187 | Secure stream protocol for serial interconnect | Siddhartha Chhabra, David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas | 2025-09-30 |
| 12430162 | User-level interprocessor interrupts | Gilbert Neiger, Asit K. Mallick, Rajesh M. Sankaran, Hisham Shafi, Vivekananthan Sanjeepan +1 more | 2025-09-30 |
| 12346695 | Copy a subset of status flags from a control and status register to a flags register | Robert Valentine, Mark J. Charney, Venkateswara Madduri | 2025-07-01 |
| 12271616 | Independently controlled DMA and CPU access to a shared memory region | Utkarsh Y. Kakaiya, David A. Koufaty, Rajesh M. Sankaran | 2025-04-08 |
| 12261941 | Creating, using, and managing protected cryptography keys | Jason W. Brandt, Steven Grobman | 2025-03-25 |
| 12253958 | System for address mapping and translation protection | Ravi L. Sahita, Gilbert Neiger, David M. Durham, Andrew V. Anderson, David A. Koufaty +7 more | 2025-03-18 |
| 12254341 | Scalable virtual machine operation inside trust domains within the trust domain architecture | Ravi L. Sahita, Tin-Cheung Kung, Barry E. Huntley, Arie Aharon | 2025-03-18 |
| 12248561 | Apparatus and method for role-based register protection for TDX-IO | Ravi L. Sahita, Utkarsh Y. Kakaiya, Abhishek Basak, Lee Albion, Filip Schmole +3 more | 2025-03-11 |
| 12248807 | Methods, apparatus, systems, and instructions to migrate protected virtual machines | Ravi L. Sahita, Dror Caspi, Vincent R. Scarlata, Sharon YANIV, Baruch Chaikin +8 more | 2025-03-11 |
| 12242391 | Processors, methods, systems, and instructions to support live migration of protected containers | Carlos V. Rozas, Mona Vij, Rebekah M. Leslie-Hurd, Krystof C. Zmudzinski, Somnath Chakrabarti +6 more | 2025-03-04 |
| 12229453 | Processors, methods, systems, and instructions to protect shadow stacks | Jason W. Brandt, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel | 2025-02-18 |
| 12222873 | Method and apparatus to enable a cache (DEVPIC) to store process specific information inside devices that support address translation service (ATS) | Rupin H. Vakharwala | 2025-02-11 |
| 12204903 | Dual sum of quadword 16×16 multiply and accumulate | Venkateswara Madduri, Cristina S. Anderson, Robert Valentine, Mark J. Charney | 2025-01-21 |
| 12189542 | Technologies for secure device configuration and management | Reshma Lal, Pradeep M. Pappachan, Luis Kida, Krystof C. Zmudzinski, Siddhartha Chhabra +5 more | 2025-01-07 |
| 12182018 | Instruction and micro-architecture support for decompression on core | Jayesh Gaur, Adarsh Chauhan, Vinodh Gopal, Sreenivas Subramoney, Wajdi K. Feghali | 2024-12-31 |
| 12153665 | Device, system and method to efficiently update a secure arbitration mode module | Baruch Chaikin | 2024-11-26 |
| 12135780 | Processor extensions to protect stacks during ring transitions | Jason W. Brandt, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak Gupta | 2024-11-05 |
| 12130738 | Compressed cache memory with decompress on fault | Jayesh Gaur, Wajdi K. Feghali, Vinodh Gopal, Utkarsh Y. Kakaiya | 2024-10-29 |
| 12112171 | Loop support extensions | Anant Vithal Nori, Shankar Balachandran, Sreenivas Subramoney, Joydeep Rakshit, Avishaii Abuhatzera +1 more | 2024-10-08 |
| 12106133 | Method and apparatus for trusted devices using Trust Domain Extensions | Ravi L. Sahita | 2024-10-01 |
| 12099841 | User timer directly programmed by application | Rajesh M. Sankaran, Gilbert Neiger, David A. Koufaty | 2024-09-24 |
| 12086653 | Software visible and controllable lock-stepping with configurable logical processor granularities | Jeff Huxel, Jeffrey G. Wiedemeier, James D. Allen, IV, Arvind Raman, Krishnakumar Ganapathy | 2024-09-10 |
| 12086424 | Memory encryption engine interface in compute express link (CXL) attached memory controllers | Siddhartha Chhabra | 2024-09-10 |
| 12038845 | Device, system and method to provide line level tagging of data at a processor cache | Siddhartha Chhabra | 2024-07-16 |
| 12032485 | 64-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s) | Gilbert Neiger, Stephen J. Robinson, Dan Baum, Ron Gabor | 2024-07-09 |