RV

Robert Valentine

IN Intel: 367 patents #13 of 30,777Top 1%
Overall (All Time): #769 of 4,157,543Top 1%
369
Patents All Time

Issued Patents All Time

Showing 25 most recent of 369 patents

Patent #TitleCo-InventorsDate
12423102 Instructions to convert from FP16 to BF8 Alexander Heinecke, Naveen Mellempudi, Mark J. Charney, Christopher J. Hughes, Evangelos Georganas +3 more 2025-09-23
12405770 Matrix transpose and multiply Menachem Adelman, Barukh Ziv, Amit Gradstein, Simon Rubanovich, Zeev Sperber +5 more 2025-09-02
12393422 Apparatus and method for vector packed signed/unsigned shift, round, and saturate Venkateswara Madduri, Mark J. Charney, Cristina S. Anderson 2025-08-19
12379927 BFLOAT16 scale and/or reduce instructions Menachem Adelman, Alexander Heinecke, Zeev Sperber, Amit Gradstein, Mark J. Charney +4 more 2025-08-05
12367045 Instructions to convert from FP16 to BF8 Alexander Heinecke, Naveen Mellempudi, Mark J. Charney, Christopher J. Hughes, Evangelos Georganas +3 more 2025-07-22
12353878 Apparatuses, methods, and systems for instructions for matrix multiplication instructions Menachem Adelman, Zeev Sperber, Amit Gradstein, Simon Rubanovich, Sagi Meller +4 more 2025-07-08
12346695 Copy a subset of status flags from a control and status register to a flags register Vedvyas Shanbhogue, Mark J. Charney, Venkateswara Madduri 2025-07-01
12314717 Systems, methods, and apparatuses for dot production operations Dan Baum, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +5 more 2025-05-27
12307250 Systems and methods for performing 16-bit floating-point matrix dot product instructions Alexander Heinecke, Mark J. Charney, Raanan Sade, Menachem Adelman, Zeev Sperber +2 more 2025-05-20
12293186 Systems and methods to store a tile register pair to memory Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +5 more 2025-05-06
12287843 Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements Dan Baum, Chen Koren, Elmoustapha Ould-Ahmed-Vall, Michael Espig, Christopher J. Hughes +3 more 2025-04-29
12282773 Systems, methods, and apparatus for tile configuration Menachem Adelman, Zeev Sperber, Mark J. Charney, Bret L. Toll, Rinat Rappoport +6 more 2025-04-22
12282525 Systems, methods, and apparatuses for matrix operations Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +5 more 2025-04-22
12277419 Apparatuses, methods, and systems for instructions to convert 16-bit floating-point formats Alexander Heinecke, Mark J. Charney, Menachem Adelman, Christopher J. Hughes, Evangelos Georganas +3 more 2025-04-15
12265826 Systems for performing instructions to quickly convert and use tiles as 1D vectors Bret L. Toll, Christopher J. Hughes, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Raanan Sade +2 more 2025-04-01
12260213 Systems, methods, and apparatuses for matrix add, subtract, and multiply Dan Baum, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +5 more 2025-03-25
12236242 Systems and methods to load a tile register pair Raanan Sade, Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke +5 more 2025-02-25
12229554 BFLOAT16 fused multiply instructions Alexander Heinecke, Menachem Adelman, Zeev Sperber, Amit Gradstein, Mark J. Charney +4 more 2025-02-18
12216734 Apparatus and method for conjugate transpose and multiply Menachem Adelman, Daniel Towner, Amit Gradstein, Mark J. Charney 2025-02-04
12204898 Interruptible and restartable matrix multiplication instructions, processors, methods, and systems Edward T. Grochowski, Asit K. Mishra, Mark J. Charney, Simon C. Steely, Jr. 2025-01-21
12204903 Dual sum of quadword 16×16 multiply and accumulate Venkateswara Madduri, Cristina S. Anderson, Mark J. Charney, Vedvyas Shanbhogue 2025-01-21
12197617 Instruction execution that broadcasts and masks data values at different levels of granularity Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Bret L. Toll, Mark J. Charney 2025-01-14
12190111 Apparatus and method for vector packed dual complex-by-complex and dual complex-by-complex conjugate multiplication Venkateswara Madduri, Mark J. Charney 2025-01-07
12182571 Systems, methods, and apparatuses for tile load, multiplication and accumulation Menachem Adelman, Milind B. Girkar, Zeev Sperber, Mark J. Charney, Bret L. Toll +10 more 2024-12-31
12182570 Apparatuses, methods, and systems for a packed data convolution instruction with shift control and width control Deepti Aggarwal, Michael Espig, Sumit Mohan, Prakaram Joshi, Richard R. Winterton 2024-12-31