Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417380 | Machine learning accelerator mechanism | Amit Bleiweiss, Anavai Ramesh, Deborah T. Marr, Jeffrey J. Cook, Srinivas Sridharan +8 more | 2025-09-16 |
| 12204898 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Edward T. Grochowski, Robert Valentine, Mark J. Charney, Simon C. Steely, Jr. | 2025-01-21 |
| 12135981 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2024-11-05 |
| 12050912 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Edward T. Grochowski, Robert Valentine, Mark J. Charney, Simon C. Steely, Jr. | 2024-07-30 |
| 12039435 | Machine learning accelerator mechanism | Amit Bleiweiss, Anavai Ramesh, Deborah T. Marr, Jeffrey J. Cook, Srinivas Sridharan +8 more | 2024-07-16 |
| 11698787 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Edward T. Grochowski, Robert Valentine, Mark J. Charney, Simon C. Steely, Jr. | 2023-07-11 |
| 11693691 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2023-07-04 |
| 11416281 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2022-08-16 |
| 11379229 | Apparatus and method for adaptable and efficient lane-wise tensor processing | Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Jeffrey J. Cook, Debbie Marr +6 more | 2022-07-05 |
| 11373088 | Machine learning accelerator mechanism | Amit Bleiweiss, Anavai Ramesh, Deborah T. Marr, Jeffrey J. Cook, Srinivas Sridharan +8 more | 2022-06-28 |
| 11113053 | Data element comparison processors, methods, systems, and instructions | Edward T. Grochowski, Jonathan Pearce, Deborah T. Marr, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall +5 more | 2021-09-07 |
| 11093277 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2021-08-17 |
| 11048508 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Edward T. Grochowski, Robert Valentine, Mark J. Charney, Simon C. Steely, Jr. | 2021-06-29 |
| 10776110 | Apparatus and method for adaptable and efficient lane-wise tensor processing | Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Jeffrey J. Cook, Deborah T. Marr +6 more | 2020-09-15 |
| 10635448 | Byte and nibble sort instructions that produce sorted destination register and destination index mapping | Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall, Deborah T. Marr | 2020-04-28 |
| 10489063 | Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication | Deborah T. Marr, Edward T. Grochowski | 2019-11-26 |
| 10423411 | Data element comparison processors, methods, systems, and instructions | Edward T. Grochowski, Jonathan Pearce, Deborah T. Marr, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall +5 more | 2019-09-24 |
| 10409613 | Processing devices to perform a key value lookup instruction | Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall, Deborah T. Marr | 2019-09-10 |
| 10275243 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Edward T. Grochowski, Robert Valentine, Mark J. Charney, Simon C. Steely, Jr. | 2019-04-30 |
| 10275247 | Apparatuses and methods to accelerate vector multiplication of vector elements having matching indices | Deborah T. Marr | 2019-04-30 |
| 10198264 | Sorting data and merging sorted data in an instruction set architecture | Deborah T. Marr, Jong Soo Park, Nadathur Rajagopalan Satish, Mikhail Smelyanskiy, Michael Anderson +3 more | 2019-02-05 |
| 9996361 | Byte and nibble sort instructions that produce sorted destination register and destination index mapping | Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall, Deborah T. Marr | 2018-06-12 |
| 9405724 | Reconfigurable apparatus for hierarchical collective networks with bypass mode | Jianping Xu, Joshua B. Fryman, David S. Dunning | 2016-08-02 |