Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JC

Jeffrey J. Cook — 25 Patents

Intel: 23 patents #1,732 of 30,777Top 6%
UNUnknown: 1 patents #29,356 of 83,584Top 40%
Portland, OR: #749 of 9,213 inventorsTop 9%
Oregon: #1,672 of 28,073 inventorsTop 6%
Overall (All Time): #158,593 of 4,157,543Top 4%
25 Patents All Time
Jeffrey J. Cook has been granted 25 US patents while listed as an inventor at Intel. The first was granted in 1983 and the most recent in September 2025. Jeffrey J. Cook ranks #158,593 of 4,157,543 US inventors in our database (top 3.8%). Patent records list Jeffrey J. Cook in Portland, OR, US.

Patents per Year

Patents granted per year, 1983 to 2025Bar chart with a peak of 5 patents in 2021.peak 51983: 1 patents19831988: 1 patents2015: 2 patents20152017: 1 patents2018: 3 patents20182019: 2 patents2020: 3 patents20202021: 5 patents2022: 3 patents20222023: 1 patents2024: 2 patents20242025: 1 patents2025

Issued Patents All Time

Showing 1–25 of 25 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12417380 Machine learning accelerator mechanism Amit Bleiweiss, Anavai Ramesh, Asit K. Mishra, Deborah T. Marr, Srinivas Sridharan +8 more 2025-09-16
12135981 Systems, methods, and apparatuses for heterogeneous computing Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more 2024-11-05 $48,202,000
12039435 Machine learning accelerator mechanism Amit Bleiweiss, Anavai Ramesh, Asit K. Mishra, Deborah T. Marr, Srinivas Sridharan +8 more 2024-07-16 $26,089,000
11693691 Systems, methods, and apparatuses for heterogeneous computing Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more 2023-07-04
11416281 Systems, methods, and apparatuses for heterogeneous computing Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more 2022-08-16 $17,788,000
11379229 Apparatus and method for adaptable and efficient lane-wise tensor processing Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Debbie Marr, Abhijit Davare +6 more 2022-07-05 $18,093,000
11373088 Machine learning accelerator mechanism Amit Bleiweiss, Anavai Ramesh, Asit K. Mishra, Deborah T. Marr, Srinivas Sridharan +8 more 2022-06-28 $15,065,000
11188341 System, apparatus and method for symbolic store address generation for data-parallel processor Srikanth Srinivasan, Jonathan Pearce, David Sheffield 2021-11-30 $30,212,000
11093277 Systems, methods, and apparatuses for heterogeneous computing Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more 2021-08-17 $29,127,000
10983773 Technologies for translation cache management in binary translation systems Paul Caprioli 2021-04-20 $53,056,000
10915328 Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Deborah T. Marr 2021-02-09 $44,388,000
10896141 Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor Jonathan Pearce, Srikanth Srinivasan, Rishiraj A. Bheda, David Sheffield, Abhijit Davare +1 more 2021-01-19 $115,732,000
10831505 Architecture and method for data parallel single program multiple data (SPMD) execution Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Deborah T. Marr, Abhijit Davare +1 more 2020-11-10 $31,576,000
10776110 Apparatus and method for adaptable and efficient lane-wise tensor processing Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Deborah T. Marr, Abhijit Davare +6 more 2020-09-15 $34,212,000
10725755 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman +10 more 2020-07-28 $26,273,000
10282182 Technologies for translation cache management in binary translation systems Paul Caprioli 2019-05-07 $24,403,000
10209989 Accelerated interlane vector reduction instructions Paul Caprioli, Abhay S. Kanhere, Muawya M. Al-Otoom 2019-02-19 $27,334,000
10089244 Hardware for miss handling from a translation protection data structure Paul Caprioli 2018-10-02 $23,827,000
9934124 Implementation of processor trace in a processor that supports binary translation Furat F. Afram, Paul Caprioli 2018-04-03 $16,515,000
9880842 Using control flow data structures to direct and track instruction execution Jayaram Bobba, Ruchira Sasanka, Abhinav Das, Arvind Krishnaswamy, David J. Sager +1 more 2018-01-30 $22,157,000
9588766 Accelerated interlane vector reduction instructions Paul Caprioli, Abhay S. Kanhere, Muawya M. Al-Otoom 2017-03-07 $9,849,000
9189233 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads Ruchira Sasanka, Abhinav Das, Jayaram Bobba, Arvind Krishnaswamy, David J. Sager +1 more 2015-11-17 $15,457,000
9170789 Analyzing potential benefits of vectorization Ruchira Sasanka, Abhinav Das, Jayaram Bobba, Michael R. Greenfield, Suresh Srinivas 2015-10-27 $18,168,000
4760215 Electrical outlet cover system Keith M. Sayre 1988-07-26
4412464 Combination can opening tool 1983-11-01