| 10725755 |
Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads |
Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled +10 more |
2020-07-28 |
$26,273,000 |
| 9880842 |
Using control flow data structures to direct and track instruction execution |
Jayaram Bobba, Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Arvind Krishnaswamy +1 more |
2018-01-30 |
$22,157,000 |
| 9672019 |
Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads |
Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled +10 more |
2017-06-06 |
$12,588,000 |
| 9189233 |
Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads |
Ruchira Sasanka, Abhinav Das, Jeffrey J. Cook, Jayaram Bobba, Arvind Krishnaswamy +1 more |
2015-11-17 |
$15,457,000 |
| RE45487 |
Processor having execution core sections operating at different clock rates |
Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton |
2015-04-21 |
|
| 8914617 |
Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register |
Shlomo Raikin, Zeev Sperber, Evgeni Krimer, Ori Lempel, Stanislav Shwartsman +2 more |
2014-12-16 |
$19,599,000 |
| 8850165 |
Method and apparatus for assigning thread priority in a processor or the like |
David William Burns, James D. Allen, IV, Michael D. Upton, Darrell D. Boggs |
2014-09-30 |
$16,330,000 |
| RE44494 |
Processor having execution core sections operating at different clock rates |
Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton |
2013-09-10 |
|
| 8347066 |
Replay instruction morphing |
Douglas M. Carmean, Thomas Toll, Karol F. Menezes |
2013-01-01 |
|
| 7987346 |
Method and apparatus for assigning thread priority in a processor or the like |
David William Burns, James D. Allen, IV, Michael D. Upton, Darrell D. Boggs |
2011-07-26 |
$21,887,000 |
| 7877583 |
Method and apparatus for assigning thread priority in a processor or the like |
David William Burns, James D. Allen, IV, Michael D. Upton, Darrell D. Boggs |
2011-01-25 |
$27,856,000 |
| 7742910 |
Mechanism for estimating and controlling di/dt-induced power supply voltage variations |
Edward T. Grochowski, Vivek Tiwari, Ian A. Young, David J. Ayers |
2010-06-22 |
$25,275,000 |
| 7454600 |
Method and apparatus for assigning thread priority in a processor or the like |
David William Burns, James D. Allen, IV, Michael D. Upton, Darrell D. Boggs |
2008-11-18 |
$14,632,000 |
| 7398372 |
Fusing load and alu operations |
Nicholas Samra, Stephan Jourdan, Glenn J. Hinton |
2008-07-08 |
$24,723,000 |
| 7236920 |
Mechanism for estimating and controlling di/dt-induced power supply voltage variations |
Edward T. Grochowski, Vivek Tiwari, Ian A. Young, David J. Ayers |
2007-06-26 |
$20,503,000 |
| 7219349 |
Multi-threading techniques for a processor utilizing a replay queue |
Amit Merchant, Darrell D. Boggs |
2007-05-15 |
$17,522,000 |
| 7200737 |
Processor with a replay system that includes a replay queue for improved throughput |
Amit Merchant, Darrell D. Boggs |
2007-04-03 |
$17,128,000 |
| 7100012 |
Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies |
— |
2006-08-29 |
$13,270,000 |
| 7089409 |
Interface to a memory system for a processor having a replay system |
Amit Merchant, Darrell D. Boggs |
2006-08-08 |
$12,359,000 |
| 7035785 |
Mechanism for estimating and controlling di/dt-induced power supply voltage variations |
Edward T. Grochowski, Vivek Tiwari, Ian A. Young, David J. Ayers |
2006-04-25 |
$12,896,000 |
| 6981129 |
Breaking replay dependency loops in a processor using a rescheduled replay queue |
Darrell D. Boggs, Douglas M. Carmean, Per Hammarlund, Francis X. McKeen, Ronak Singhal |
2005-12-27 |
$17,238,000 |
| 6952764 |
Stopping replay tornadoes |
Stephan Jourdan, Per Hammarlund |
2005-10-04 |
$23,554,000 |
| 6928647 |
Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor |
— |
2005-08-09 |
$18,014,000 |
| 6925550 |
Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection |
Eric Sprangle, Michael Haertel |
2005-08-02 |
$20,766,000 |
| 6880069 |
Replay instruction morphing |
Douglas M. Carmean, Thomas Toll, Karol F. Menezes |
2005-04-12 |
$19,475,000 |
