Issued Patents All Time
Showing 25 most recent of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12135981 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2024-11-05 |
| 12073214 | Systems, apparatuses, and methods for chained fused multiply add | Jesus Corbal, Robert Valentine, Roman S. Dubtsov, Nikita A. Shustrov, Mark J. Charney +4 more | 2024-08-27 |
| 11693691 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2023-07-04 |
| 11487541 | Systems, apparatuses, and methods for chained fused multiply add | Jesus Corbal, Robert Valentine, Roman S. Dubtsov, Nikita A. Shustrov, Mark J. Charney +4 more | 2022-11-01 |
| 11416281 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2022-08-16 |
| 11093277 | Systems, methods, and apparatuses for heterogeneous computing | Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman +22 more | 2021-08-17 |
| 10853065 | Systems, apparatuses, and methods for chained fused multiply add | Jesus Corbal, Robert Valentine, Roman S. Dubtsov, Nikita A. Shustrov, Mark J. Charney +4 more | 2020-12-01 |
| 10146535 | Systems, apparatuses, and methods for chained fused multiply add | Jesus Corbal, Robert Valentine, Roman S. Dubtsov, Nikita A. Shustrov, Mark J. Charney +4 more | 2018-12-04 |
| 10133577 | Vector mask driven clock gating for power efficiency of a processor | Jesus Corbal, Dennis R. Bradford, Jonathan C. Hall, Brian J. Hickmann, Dror Markovich +1 more | 2018-11-20 |
| 9792115 | Super multiply add (super MADD) instructions with three scalar terms | Jesus Corbal, Andrew T. Forsyth, Lisa K. Wu, Eric Sprangle | 2017-10-17 |
| 9766886 | Instruction and logic to provide vector linear interpolation functionality | Jesus Corbal, Andrew T. Forsyth, Lisa K. Wu | 2017-09-19 |
| 9733935 | Super multiply add (super madd) instruction | Jesus Corbal, Andrew T. Forsyth, Roger Espasa, Manel Fernandez | 2017-08-15 |
| 9654143 | Consecutive bit error detection and correction | Guillem Sole, Roger Espasa, Sorin Iacobovici, Brian J. Hickmann, Wei Wu | 2017-05-16 |
| 9639355 | Functional unit capable of executing approximations of functions | Alex Pineiro, Brian J. Hickmann | 2017-05-02 |
| 9588765 | Instruction and logic for multiplier selectors for merging math functions | — | 2017-03-07 |
| 9465580 | Math circuit for estimating a transcendental function | Jose-Alejandro Pineiro, Simon Rubanovich, Benny Eitan, Amit Gradstein | 2016-10-11 |
| 9323500 | Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values | Brian J. Hickmann, Dennis R. Bradford | 2016-04-26 |
| 9152382 | Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values | Brian J. Hickmann, Dennis R. Bradford | 2015-10-06 |
| 9141586 | Method, apparatus, system for single-path floating-point rounding flow that supports generation of normals/denormals and associated status flags | Warren E. Ferguson, Brian J. Hickmann | 2015-09-22 |
| RE45487 | Processor having execution core sections operating at different clock rates | David J. Sager, Glenn J. Hinton, Michael D. Upton | 2015-04-21 |
| 8676871 | Functional unit capable of executing approximations of functions | Alex Pineiro, Brian J. Hickmann | 2014-03-18 |
| RE44494 | Processor having execution core sections operating at different clock rates | David J. Sager, Glenn J. Hinton, Michael D. Upton | 2013-09-10 |
| 7428568 | Symmetric cascaded domino carry generate circuit | — | 2008-09-23 |
| 7392277 | Cascaded domino four-to-two reducer circuit and method | — | 2008-06-24 |
| 7325025 | Look-ahead carry adder circuit | — | 2008-01-29 |