| 10831477 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Doron Orenstein |
2020-11-10 |
$31,576,000 |
| 10649733 |
Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions |
Cristina S. Anderson, Zeev Sperber, Simon Rubanovich, Amit Gradstein |
2020-05-12 |
$29,489,000 |
| 10514916 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Doron Orenstein |
2019-12-24 |
$26,956,000 |
| 10514917 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Doron Orenstein |
2019-12-24 |
$26,956,000 |
| 10514918 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Doron Orenstein |
2019-12-24 |
$26,956,000 |
| 10509652 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Doron Orenstein |
2019-12-17 |
$31,829,000 |
| 10318244 |
Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions |
Cristina S. Anderson, Zeev Sperber, Simon Rubanovich, Amit Gradstein |
2019-06-11 |
$16,707,000 |
| 10275216 |
Floating point scaling processors, methods, systems, and instructions |
Cristina S. Anderson, Amit Gradstein, Robert Valentine, Simon Rubanovich |
2019-04-30 |
$31,713,000 |
| 10228909 |
Floating point scaling processors, methods, systems, and instructions |
Cristina S. Anderson, Amit Gradstein, Robert Valentine, Simon Rubanovich |
2019-03-12 |
$21,255,000 |
| 10209986 |
Floating point rounding processors, methods, systems, and instructions |
Jesus Corbal San Adrian, Cristina S. Anderson, Robert Valentine, Bret L. Toll, Amit Gradstein +1 more |
2019-02-19 |
$27,334,000 |
| 10120684 |
Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memory |
Doron Orenstien, Zeev Sperber, Robert Valentine |
2018-11-06 |
$18,970,000 |
| 10089076 |
Floating point scaling processors, methods, systems, and instructions |
Cristina S. Anderson, Amit Gradstein, Robert Valentine, Simon Rubanovich |
2018-10-02 |
$23,827,000 |
| 9921807 |
Floating point scaling processors, methods, systems, and instructions |
Cristina S. Anderson, Amit Gradstein, Robert Valentine, Simon Rubanovich |
2018-03-20 |
$13,809,000 |
| 9672034 |
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits |
Zeev Sperber, Robert Valentine, Doron Orenstein |
2017-06-06 |
$12,588,000 |
| 9606770 |
Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions |
Cristina S. Anderson, Zeev Sperber, Simon Rubanovich, Amit Gradstein |
2017-03-28 |
$8,391,000 |
| 9529592 |
Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation |
Doron Orenstien, Zeev Sperber, Bob Valentine |
2016-12-27 |
$11,980,000 |
| 9465580 |
Math circuit for estimating a transcendental function |
Jose-Alejandro Pineiro, Simon Rubanovich, Amit Gradstein, Thomas D. Fletcher |
2016-10-11 |
$13,479,000 |
| 9448765 |
Floating point scaling processors, methods, systems, and instructions |
Christina Anderson, Amit Gradstein, Robert Valentine, Simon Rubanovich |
2016-09-20 |
$10,814,000 |
| 9389858 |
Orderly storing of corresponding packed bytes from first and second source registers in result register |
Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier |
2016-07-12 |
$10,128,000 |
| 9361100 |
Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements |
Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier |
2016-06-07 |
$9,646,000 |
| 9223572 |
Interleaving half of packed data elements of size specified in instruction and stored in two source registers |
Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier |
2015-12-29 |
$8,962,000 |
| 9182983 |
Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers |
Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier |
2015-11-10 |
$14,197,000 |
| 9141387 |
Processor executing unpack and pack instructions specifying two source packed data operands and saturation |
Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier |
2015-09-22 |
$9,820,000 |
| 9116687 |
Packing in destination register half of each element with saturation from two source packed data registers |
Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier |
2015-08-25 |
$14,120,000 |
| 9042652 |
Techniques for connected component labeling |
Niraj Gupta, Oren Agam, Mostafa Hagog |
2015-05-26 |
$20,586,000 |
