Issued Patents All Time
Showing 26–50 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9015453 | Packing odd bytes from two source registers of packed data | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2015-04-21 |
| 8984043 | Multiplying and adding matrices | Boris Ginzburg, Simon Rubanovich | 2015-03-17 |
| 8914430 | Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions | Amit Gradstein, Cristina S. Anderson, Zeev Sperber, Simon Rubanovich | 2014-12-16 |
| 8914613 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits | Zeev Sperber, Robert Valentine, Doron Orenstein | 2014-12-16 |
| 8838946 | Packing lower half bits of signed data elements in two source registers in a destination register with saturation | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2014-09-16 |
| 8793299 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Carole Dulong, Eiichi Kowashi +1 more | 2014-07-29 |
| 8793475 | Method and apparatus for unpacking and moving packed data | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2014-07-29 |
| 8769249 | Instructions with floating point control override | Cristina S. Anderson, Simon Rubanovich | 2014-07-01 |
| 8745119 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Carole Dulong, Eiichi Kowashi +1 more | 2014-06-03 |
| 8725787 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Carole Dulong, Eiichi Kowashi +1 more | 2014-05-13 |
| 8706789 | Performing reciprocal instructions with high accuracy | Zeev Sperber, Cristina S. Anderson, Simon Rubanovich, Amit Gradstein | 2014-04-22 |
| 8694758 | Mixing instructions with different register sizes | Doron Orenstien, Zeev Sperber, Robert Valentine | 2014-04-08 |
| 8639914 | Packing signed word elements from two source registers to saturated signed byte elements in destination register | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2014-01-28 |
| 8626814 | Method and apparatus for performing multiply-add operations on packed data | Alexander Peleg, Milland Mittal, Larry M. Mennemeier, Carole Dulong, Eiichi Kowashi +1 more | 2014-01-07 |
| 8601246 | Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2013-12-03 |
| 8521994 | Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2013-08-27 |
| 8495123 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Carole Dulong, Eiichi Kowashi +1 more | 2013-07-23 |
| 8495346 | Processor executing pack and unpack instructions | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2013-07-23 |
| 8396915 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Carole Dulong, Eiichi Kowashi +1 more | 2013-03-12 |
| 8327120 | Instructions with floating point control override | Cristina S. Anderson, Simon Rubanovich | 2012-12-04 |
| 8190867 | Packing two packed signed data in registers with saturation | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2012-05-29 |
| 8185571 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Carole Dulong, Eiichi Kowashi +1 more | 2012-05-22 |
| 8078836 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits | Zeev Sperber, Robert Valentine, Doron Orenstein | 2011-12-13 |
| 7966482 | Interleaving saturated lower half of data elements from two source registers of packed data | Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier | 2011-06-21 |
| 7882325 | Method and apparatus for a double width load using a single width load port | Zeev Sperber, Robert Valentine, Ehud Cohen, Doron Orenstien | 2011-02-01 |