| 11048507 |
Compressed instruction format |
Robert Valentine, Bret L. Toll |
2021-06-29 |
$34,663,000 |
| 10831477 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Benny Eitan |
2020-11-10 |
$31,576,000 |
| 10514918 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Benny Eitan |
2019-12-24 |
$26,956,000 |
| 10514916 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Benny Eitan |
2019-12-24 |
$26,956,000 |
| 10514917 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Benny Eitan |
2019-12-24 |
$26,956,000 |
| 10509652 |
In-lane vector shuffle instructions |
Zeev Sperber, Robert Valentine, Benny Eitan |
2019-12-17 |
$31,829,000 |
| 10095515 |
Compressed instruction format |
Robert Valentine, Bret L. Toll |
2018-10-09 |
$20,353,000 |
| 9672034 |
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits |
Zeev Sperber, Robert Valentine, Benny Eitan |
2017-06-06 |
$12,588,000 |
| 9569208 |
Compressed instruction format |
Robert Valentine, Brett L. Toll |
2017-02-14 |
$9,787,000 |
| 9235415 |
Permute operations with flexible zero control |
Cristina S. Anderson, Mark Buxton, Robert Valentine |
2016-01-12 |
$15,498,000 |
| 9086872 |
Unpacking packed data in multiple lanes |
Asaf Hargil |
2015-07-21 |
$13,511,000 |
| 9081562 |
Unpacking packed data in multiple lanes |
Asaf Hargil |
2015-07-14 |
$20,297,000 |
| 8914613 |
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits |
Zeev Sperber, Robert Valentine, Benny Eitan |
2014-12-16 |
$19,599,000 |
| 8756403 |
Compressed instruction format |
Robert Valentine, Brett L. Toll |
2014-06-17 |
$25,629,000 |
| 8281109 |
Compressed instruction format |
Robert Valentine, Bret L. Toll |
2012-10-02 |
$10,164,000 |
| 8078836 |
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits |
Zeev Sperber, Robert Valentine, Benny Eitan |
2011-12-13 |
$17,618,000 |
| 8078831 |
Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors |
Hong Wang, Perry Wang, Jeffery A. Brown, Per Hammarlund, George Z. Chrysos +2 more |
2011-12-13 |
$17,618,000 |
| 7849465 |
Programmable event driven yield mechanism which may activate service threads |
Xiang Zou, Hong Wang, Scott Dion Rodgers, Darrell D. Boggs, Bryant Bigbee +8 more |
2010-12-07 |
$26,454,000 |
| 7844801 |
Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors |
Hong Wang, Perry Wang, Jeffery A. Brown, Per Hammarlund, George Z. Chrysos +2 more |
2010-11-30 |
$13,201,000 |
| 7721129 |
Method and apparatus for reducing clock frequency during low workload periods |
Itamar Kazachinsky |
2010-05-18 |
$11,091,000 |
| 7437581 |
Method and apparatus for varying energy per instruction according to the amount of available parallelism |
Edward T. Grochowski, John Shen, Hong Wang, Gad Sheaffer, Ronny Ronen +1 more |
2008-10-14 |
$13,671,000 |
| 7051227 |
Method and apparatus for reducing clock frequency during low workload periods |
Itamar Kazachinsky |
2006-05-23 |
$10,027,000 |
| 6944720 |
Memory system for multiple data types |
Zeev Sperber, Guy Peled, Ehud Cohen, Gabi Malka |
2005-09-13 |
$17,645,000 |
| 6886105 |
Method and apparatus for resuming memory operations from a low latency wake-up low power state |
Opher Kahn |
2005-04-26 |
$30,166,000 |
| 6724391 |
Mechanism for implementing Z-compression transparently |
Guy Peled, Zeev Sperber, Guiliermo Savranski |
2004-04-20 |
$26,995,000 |
