Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11048507 | Compressed instruction format | Robert Valentine, Bret L. Toll | 2021-06-29 |
| 10831477 | In-lane vector shuffle instructions | Zeev Sperber, Robert Valentine, Benny Eitan | 2020-11-10 |
| 10514918 | In-lane vector shuffle instructions | Zeev Sperber, Robert Valentine, Benny Eitan | 2019-12-24 |
| 10514916 | In-lane vector shuffle instructions | Zeev Sperber, Robert Valentine, Benny Eitan | 2019-12-24 |
| 10514917 | In-lane vector shuffle instructions | Zeev Sperber, Robert Valentine, Benny Eitan | 2019-12-24 |
| 10509652 | In-lane vector shuffle instructions | Zeev Sperber, Robert Valentine, Benny Eitan | 2019-12-17 |
| 10095515 | Compressed instruction format | Robert Valentine, Bret L. Toll | 2018-10-09 |
| 9672034 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits | Zeev Sperber, Robert Valentine, Benny Eitan | 2017-06-06 |
| 9569208 | Compressed instruction format | Robert Valentine, Brett L. Toll | 2017-02-14 |
| 9235415 | Permute operations with flexible zero control | Cristina S. Anderson, Mark Buxton, Robert Valentine | 2016-01-12 |
| 9086872 | Unpacking packed data in multiple lanes | Asaf Hargil | 2015-07-21 |
| 9081562 | Unpacking packed data in multiple lanes | Asaf Hargil | 2015-07-14 |
| 8914613 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits | Zeev Sperber, Robert Valentine, Benny Eitan | 2014-12-16 |
| 8756403 | Compressed instruction format | Robert Valentine, Brett L. Toll | 2014-06-17 |
| 8281109 | Compressed instruction format | Robert Valentine, Bret L. Toll | 2012-10-02 |
| 8078836 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits | Zeev Sperber, Robert Valentine, Benny Eitan | 2011-12-13 |
| 8078831 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors | Hong Wang, Perry Wang, Jeffery A. Brown, Per Hammarlund, George Z. Chrysos +2 more | 2011-12-13 |
| 7849465 | Programmable event driven yield mechanism which may activate service threads | Xiang Zou, Hong Wang, Scott Dion Rodgers, Darrell D. Boggs, Bryant Bigbee +8 more | 2010-12-07 |
| 7844801 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors | Hong Wang, Perry Wang, Jeffery A. Brown, Per Hammarlund, George Z. Chrysos +2 more | 2010-11-30 |
| 7721129 | Method and apparatus for reducing clock frequency during low workload periods | Itamar Kazachinsky | 2010-05-18 |
| 7437581 | Method and apparatus for varying energy per instruction according to the amount of available parallelism | Edward T. Grochowski, John Shen, Hong Wang, Gad Sheaffer, Ronny Ronen +1 more | 2008-10-14 |
| 7051227 | Method and apparatus for reducing clock frequency during low workload periods | Itamar Kazachinsky | 2006-05-23 |
| 6944720 | Memory system for multiple data types | Zeev Sperber, Guy Peled, Ehud Cohen, Gabi Malka | 2005-09-13 |
| 6886105 | Method and apparatus for resuming memory operations from a low latency wake-up low power state | Opher Kahn | 2005-04-26 |
| 6724391 | Mechanism for implementing Z-compression transparently | Guy Peled, Zeev Sperber, Guiliermo Savranski | 2004-04-20 |