Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10656697 | Processor core power event tracing | Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree Chabukswar +4 more | 2020-05-19 |
| 9910475 | Processor core power event tracing | Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree Chabukswar +4 more | 2018-03-06 |
| 9696997 | Real time instruction trace processors, methods, and systems | Tsvika Kurts, Ofer Levy, Gabi Malka, Zeev Sperber, Jason W. Brandt | 2017-07-04 |
| 9612938 | Providing status of a processing device with periodic synchronization point in instruction tracing system | Frank Binns, Matthew C. Merten, Mayank Bomb, Beeman C. Strong, Peter Lachner +3 more | 2017-04-04 |
| 9262163 | Real time instruction trace processors, methods, and systems | Tsvika Kurts, Ofer Levy, Gabi Malka, Zeev Sperber, Jason W. Brandt | 2016-02-16 |
| 9189360 | Processor that records tracing data in non contiguous system memory slices | Beeman C. Strong, Jason W. Brandt, Tsvika Kurts, Peter Lachner, Stephen J. Robinson +1 more | 2015-11-17 |
| 9063729 | Device, system and method of generating an execution instruction based on a memory-access instruction | Alon Naveh, Eliezer Weissmann, Iris Sorani, Yair Kazarinov | 2015-06-23 |
| 8281083 | Device, system and method of generating an execution instruction based on a memory-access instruction | Alon Naveh, Eliezer Weissmann, Iris Sorani, Yair Kazarinov | 2012-10-02 |
| 7721129 | Method and apparatus for reducing clock frequency during low workload periods | Doron Orenstein | 2010-05-18 |
| 7051227 | Method and apparatus for reducing clock frequency during low workload periods | Doron Orenstein | 2006-05-23 |
| 6570573 | Method and apparatus for pre-fetching vertex buffers in a computer system | Zeev Offen | 2003-05-27 |
| 5379396 | Write ordering for microprocessor depending on cache hit and write buffer content | Simcha Gochman, Michael Kagan | 1995-01-03 |
| 5301298 | Processor for multiple cache coherent protocols | Michael Kagan, Simcha Gochman, Tal Gat | 1994-04-05 |