Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12339723 | Controlling operating voltage of a processor | Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Inder M. Sodhi | 2025-06-24 |
| 11822409 | Controlling operating frequency of a processor | Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Inder M. Sodhi | 2023-11-21 |
| 11507167 | Controlling operating voltage of a processor | Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Inder M. Sodhi | 2022-11-22 |
| 11175712 | Controlling operating voltage of a processor | Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Inder M. Sodhi | 2021-11-16 |
| 10401928 | Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods | Ivan Herrera Mejia | 2019-09-03 |
| 10394300 | Controlling operating voltage of a processor | Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Inder M. Sodhi | 2019-08-27 |
| 10204051 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2019-02-12 |
| 10078590 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2018-09-18 |
| 9996135 | Controlling operating voltage of a processor | Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Inder M. Sodhi | 2018-06-12 |
| 9946650 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2018-04-17 |
| 9898298 | Context save and restore | Inder M. Sodhi | 2018-02-20 |
| 9665488 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2017-05-30 |
| 9594413 | Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods | Ivan Herrera Mejia | 2017-03-14 |
| 9395784 | Independently controlling frequency of plurality of power domains in a processor system | Inder M. Sodhi, Sanjeev Jahagirdar, Ryan D. Wells, Shalini Sharma, Ken Drottar | 2016-07-19 |
| 9367114 | Controlling operating voltage of a processor | Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Inder M. Sodhi | 2016-06-14 |
| 9250901 | Execution context swap between heterogeneous functional hardware units | Inder M. Sodhi, Marc Torrant, Michael Mishaeli, Ashish V. Choubal, Jason W. Brandt | 2016-02-02 |
| 9239789 | Method and apparatus for monitor and MWAIT in a distributed cache architecture | Alon Naveh, Iris Sorani | 2016-01-19 |
| 9081687 | Method and apparatus for MONITOR and MWAIT in a distributed cache architecture | Alon Naveh, Iris Sorani | 2015-07-14 |
| 9035959 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2015-05-19 |
| 9035962 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2015-05-19 |
| 9035960 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2015-05-19 |
| 8954771 | Split deep power down of I/O module | Inder M. Sodhi, Amjad Khan, Ryan D. Wells | 2015-02-10 |
| 8643660 | Technique to share information among different cache coherency domains | Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn | 2014-02-04 |
| 8347035 | Posting weakly ordered transactions | Geeyarpuram N. Santhanakrishnan, Julius Mandelblat, Ehud Cohen, Larisa Novakovsky, Michelle J. Moravan +2 more | 2013-01-01 |
| 8151061 | Ensuring coherence between graphics and display domains | Robert L. Farrell, Michael J. Muchnick, Altug Koker, Ariel Berkovits | 2012-04-03 |