GS

Geeyarpuram N. Santhanakrishnan

IN Intel: 13 patents #3,143 of 30,777Top 15%
📍 Mercer Island, WA: #150 of 829 inventorsTop 20%
🗺 Washington: #7,816 of 76,902 inventorsTop 15%
Overall (All Time): #358,661 of 4,157,543Top 9%
13
Patents All Time

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
12189479 Apparatus and method for detecting and recovering from data fetch errors Theodros Yigzaw, Ganapati Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli +5 more 2025-01-07
11048587 Apparatus and method for detecting and recovering from data fetch errors Theodros Yigzaw, Ganapati Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli +5 more 2021-06-29
10223204 Apparatus and method for detecting and recovering from data fetch errors Theodros Yigzaw, Ganapati Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli +5 more 2019-03-05
9910807 Ring protocol for low latency interconnect switch Robert G. Blankenship, Yen-Cheng Liu, Bahaa Fahim, Ganapati Srinivasa 2018-03-06
9639490 Ring protocol for low latency interconnect switch Robert G. Blankenship, Yen-Cheng Liu, Bahaa Fahim, Ganapati Srinivasa 2017-05-02
9575895 Providing common caching agent for core and integrated input/output (IO) module Yen-Cheng Liu, Robert G. Blankenship, Ganapati Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur +1 more 2017-02-21
9448879 Apparatus and method for implement a multi-level memory hierarchy Theodros Yigzaw, Oded Lempel, Hisham Shafi, Jose A. Vargas, Ganapati Srinivasa +6 more 2016-09-20
8984228 Providing common caching agent for core and integrated input/output (IO) module Yen-Cheng Liu, Robert G. Blankenship, Ganapati Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur +1 more 2015-03-17
8347035 Posting weakly ordered transactions Julius Mandelblat, Ehud Cohen, Larisa Novakovsky, Zeev Offen, Michelle J. Moravan +2 more 2013-01-01
8275942 Performance prioritization in multi-threaded processors Theodros Yigzaw, Mark Rowland, Ganapati Srinivasa 2012-09-25
8079031 Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric Michael Cole, Mark Rowland, Ganapati Srinivasa 2011-12-13
8074131 Generic debug external connection (GDXC) for high integration integrated circuits Tsvika Kurts, Guillermo Savransky, Jason Ratner, Eilon Hazan, Daniel Skaba +1 more 2011-12-06
7353338 Credit mechanism for multiple banks of shared cache Yen-Cheng Liu, Krishnakanth V. Sistla, George Cai, Ganapati Srinivasa 2008-04-01