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USPTO Patent Rankings Data through Dec 31, 2025
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Mark Rowland — 15 Patents

Intel: 8 patents #4,914 of 30,777Top 20%
SFState Farm: 7 patents #293 of 1,137Top 30%
Beaverton, OR: #407 of 3,140 inventorsTop 15%
Oregon: #2,909 of 28,073 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Mark Rowland has been granted 15 US patents while listed as an inventor at Intel. The first was granted in 2007 and the most recent in December 2019. Mark Rowland ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Mark Rowland in Beaverton, OR, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
D870150 Display screen with a graphical user interface for menu of insurance offerings Erin Barthold, Brittany Boyer, Brian Marczak, Lisa G. Rossi, Ben Schoer +2 more 2019-12-17
D870149 Display screen with a graphical user interface for various insurance offerings Erin Barthold, Brittany Boyer, Brian Marczak, Lisa G. Rossi, Ben Schoer +2 more 2019-12-17
D869487 Display screen with a graphical user interface for menu of insurance offerings Erin Barthold, Brittany Boyer, Brian Marczak, Lisa G. Rossi, Ben Schoer +2 more 2019-12-10
D859462 Display screen with a graphical user interface for menu of insurance offerings Erin Barthold, Brittany Boyer, Brian Marczak, Lisa G. Rossi, Ben Schoer +2 more 2019-09-10
D859454 Display screen with a graphical user interface for finding an insurance agent Erin Barthold, Brittany Boyer, Brian Marczak, Lisa G. Rossi, Ben Schoer +2 more 2019-09-10
D837248 Display screen with a graphical user interface for compressed insurance exploration menu Brittany Boyer, Erin Barthold, Brian Marczak, Lisa G. Rossi, Ben Schoer +2 more 2019-01-01
D837249 Display screen with a graphical user interface for expanded insurance exploration menu Erin Barthold, Brittany Boyer, Brian Marczak, Lisa G. Rossi, Ben Schoer +2 more 2019-01-01
9760409 Dynamically modifying a power/performance tradeoff based on a processor utilization Krishnakanth V. Sistla, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski +3 more 2017-09-12 $10,213,000
9501129 Dynamically adjusting power of non-core processor circuitry including buffer circuitry Krishnakanth V. Sistla, Dean Mulla, Vivek Garg, Suresh Doraiswamy, Ganapati Srinivasa +1 more 2016-11-22 $9,157,000
9372524 Dynamically modifying a power/performance tradeoff based on processor utilization Krishnakanth V. Sistla, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski +3 more 2016-06-21 $13,200,000
8914650 Dynamically adjusting power of non-core processor circuitry including buffer circuitry Krishnakanth V. Sistla, Dean Mulla, Vivek Garg, Suresh Doraiswamy, Ganapati Srinivasa +1 more 2014-12-16 $19,599,000
8275942 Performance prioritization in multi-threaded processors Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa 2012-09-25 $23,105,000
8079031 Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric Geeyarpuram N. Santhanakrishnan, Michael Cole, Ganapati Srinivasa 2011-12-13 $17,618,000
7711901 Method, system, and apparatus for an hierarchical cache line replacement Christopher Shannon, Ganapati Srinivasa 2010-05-04 $15,201,000
7277992 Cache eviction technique for reducing cache eviction traffic Christopher Shannon, Ganapati Srinivasa 2007-10-02 $20,761,000