Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Dean Mulla — 47 Patents

Intel: 32 patents #1,151 of 30,777Top 4%
HP: 17 patents #982 of 16,619Top 6%
Saratoga, CA: #189 of 2,933 inventorsTop 7%
California: #8,880 of 386,348 inventorsTop 3%
Overall (All Time): #59,703 of 4,157,543Top 2%
47 Patents All Time
Dean Mulla has been granted 47 US patents while listed as an inventor at Intel. The first was granted in 1996 and the most recent in September 2024. Dean Mulla ranks #59,703 of 4,157,543 US inventors in our database (top 1.4%). Patent records list Dean Mulla in Saratoga, CA, US.

Issued Patents All Time

Showing 1–25 of 47 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12093100 Hierarchical power management apparatus and method Vivek Garg, Ankush Varma, Krishnakanth V. Sistla, Nikhil Gupta, Nikethan Shivanand Baligar +20 more 2024-09-17 $19,251,000
11016556 Instruction and logic for parallel multi-step power management flow Alexander Gendler, Doron Rajwan, Tal Kuzi, Ariel Szapiro, Nir Tell 2021-05-25 $32,857,000
10946866 Core tightly coupled lockstep for high functional safety Bahaa Fahim, Riccardo Mariani, Robert Gottlieb 2021-03-16 $38,556,000
10365707 Instruction and logic for parallel multi-step power management flow Alexander Gendler, Doron Rajwan, Tal Kuzi, Ariel Szapiro, Nir Tell 2019-07-30 $29,864,000
9910470 Controlling telemetry data communication in a processor Vivek Garg, Alexander Gendler, Arvind Raman, Ashish V. Choubal, Krishnakanth V. Sistla +3 more 2018-03-06 $18,859,000
9753525 Systems and methods for core droop mitigation based on license state Nazar Haider, Allen W. Chu 2017-09-05 $9,844,000
9720491 Tracking missed periodic actions across state domains Daniel Borkowski, Krishnakanth V. Sistla, Victor Wu, Manev Luthra 2017-08-01 $11,137,000
9710041 Masking a power state of a core of a processor Alexander Gendler, Larisa Novakovsky, Krishnakanth V. Sistla, Vivek Garg, Ashish V. Choubal +2 more 2017-07-18 $6,909,000
9501129 Dynamically adjusting power of non-core processor circuitry including buffer circuitry Krishnakanth V. Sistla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa +1 more 2016-11-22 $9,157,000
8914650 Dynamically adjusting power of non-core processor circuitry including buffer circuitry Krishnakanth V. Sistla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa +1 more 2014-12-16 $19,599,000
8769295 Computing system feature activation mechanism Rahul Khanna, Keith Robert Pflederer 2014-07-01 $13,029,000
7680990 Superword memory-access instructions for data processor Donald Soltis, Dale Morris, Achmed R. Zahir, Amy O'Donnell, Allan D. Knies 2010-03-16 $13,845,000
7376877 Combined tag and data ECC for enhanced soft error recovery from cache tag errors Nhon Quach, John Fu, Sunny C. Huang, Jeen-Yuan Miin 2008-05-20 $25,766,000
7376775 Apparatus, system, and method to enable transparent memory hot plug/remove Lily P. Looi, Stanley Steven Kulick, Ashish Gupta, Keith Robert Pflederer, Shivnandan Kaushik +2 more 2008-05-20 $25,766,000
7159046 Method and apparatus for configuring communication between devices in a computer system Keith Robert Pflederer 2007-01-02
6948094 Method of correcting a machine check error Len Schultz, Nhon Quach, Jim Hays, John Fu 2005-09-20 $19,561,000
6874116 Masking error detection/correction latency in multilevel cache transfers Shawn Walker, Donald Soltis, Terry L Lyon 2005-03-29 $9,208,000
6832308 Apparatus and method for instruction fetch unit William G. Sicaras, Joe R. Butler, Don R. Weiss, Lakshmikant Mamileti, Reid J. Reidlinger 2004-12-14
6826573 Method and apparatus for queue issue pointer William G. Sicaras 2004-11-30 $36,984,000
6772383 Combined tag and data ECC for enhanced soft error recovery from cache tag errors Nhon Quach, John Fu, Sunny C. Huang, Jeen-Yuan Miin 2004-08-03 $15,005,000
6725339 Processing ordered data requests to a memory John Fu, Gregory S. Mathews, Stuart E. Sailer, Jeng-Jye Shaw 2004-04-20 $26,995,000
6704820 Unified cache port consolidation Shawn Walker, Terry L Lyon 2004-03-09 $13,217,000
6687262 Distributed MUX scheme for bi-endian rotator circuit Daming Jin, Douglas J. Cutter, Thomas Grutkowski 2004-02-03
6647464 System and method utilizing speculative cache access for improved performance Reid James Riedlinger, Tom Grutkowski 2003-11-11 $9,928,000
6591393 Masking error detection/correction latency in multilevel cache transfers Shawn Walker, Donald Soltis, Terry L Lyon 2003-07-08 $20,812,000