Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10628615 | Asset protection of integrated circuits during transport | Ramamurthy Krithivas, Bradley A. Burres | 2020-04-21 |
| 10193826 | Shared mesh | Bahaa Fahim, Yen-Cheng Liu, Chung-Chi Wang, Terry C. Huang, Tejpal Singh +2 more | 2019-01-29 |
| 9996711 | Asset protection of integrated circuits during transport | Ramamurthy Krithivas, Bradley A. Burres | 2018-06-12 |
| 9317089 | Mesh performance improvement using dual voltage data transfer | Nazar Haider | 2016-04-19 |
| 7930539 | Computer system resource access control | Rohit Bhatia, Eric Delano | 2011-04-19 |
| 7680990 | Superword memory-access instructions for data processor | Dale Morris, Dean Mulla, Achmed R. Zahir, Amy O'Donnell, Allan D. Knies | 2010-03-16 |
| 7600101 | Multithreaded hardware systems and methods | — | 2009-10-06 |
| 7543113 | Cache memory system and method capable of adaptively accommodating various memory line sizes | Shawn Walker, Karl Brummel | 2009-06-02 |
| 7421689 | Processor-architecture for facilitating a virtual machine monitor | Jonathan Ross, Dale Morris, Rohit Bhatia, Eric Delano | 2008-09-02 |
| 7343479 | Method and apparatus for implementing two architectures in a chip | Patrick Knebel, Kevin Safford, Joel D. Lamb, Stephen R. Undy, Russell C. Brockmann | 2008-03-11 |
| 7287185 | Architectural support for selective use of high-reliability mode in a computer system | Kevin Safford | 2007-10-23 |
| 7281147 | Systems and methods for variable control of power dissipation in a pipelined processor | Glenn T. Colon-Bonet | 2007-10-09 |
| 7243215 | System and method for utilizing a scoreboard to indicate information pertaining to pending register writes | Ronny Lee Arnold | 2007-07-10 |
| 7237144 | Off-chip lockstep checking | Kevin Safford, Eric Delano | 2007-06-26 |
| 7213134 | Using thread urgency in determining switch events in a temporal multithreaded processor unit | Rohit Bhatia | 2007-05-01 |
| 7213132 | System and method for providing predicate data to multiple pipeline stages | Gary J Benjamin, Ronny Lee Arnold | 2007-05-01 |
| 7146490 | Processing system and method for efficiently enabling detection of data hazards for long latency instructions | Ronny Lee Arnold | 2006-12-05 |
| 7047437 | Method and system for detecting dropped micro-packets | Samuel D. Naffziger | 2006-05-16 |
| 7028167 | Core parallel execution with different optimization characteristics to decrease dynamic execution path | Eric Delano | 2006-04-11 |
| 7028196 | System, method and apparatus for conserving power consumed by a system having a processor integrated circuit | Samuel D. Naffziger | 2006-04-11 |
| 6944751 | Register renaming to reduce bypass and increase apparent physical register size | Eric Fetzer, Stephen R. Undy | 2005-09-13 |
| 6883150 | Automatic manufacturing test case generation method and system | Robert Weidner, Stephen R. Undy, Kevin Safford | 2005-04-19 |
| 6874116 | Masking error detection/correction latency in multilevel cache transfers | Shawn Walker, Dean Mulla, Terry L Lyon | 2005-03-29 |
| 6871264 | System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits | — | 2005-03-22 |
| 6832300 | Methods and apparatus for control of asynchronous cache | Samuel D. Naffziger | 2004-12-14 |