Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7356674 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine | Anuj Dua, James E. McCormick, Jr., Barry J. Arnold, Russell C. Brockmann, David Carl Kubicek +1 more | 2008-04-08 |
| 7343479 | Method and apparatus for implementing two architectures in a chip | Patrick Knebel, Kevin Safford, Donald Soltis, Joel D. Lamb, Russell C. Brockmann | 2008-03-11 |
| 6944751 | Register renaming to reduce bypass and increase apparent physical register size | Eric Fetzer, Donald Soltis | 2005-09-13 |
| 6883150 | Automatic manufacturing test case generation method and system | Donald Soltis, Robert Weidner, Kevin Safford | 2005-04-19 |
| 6799263 | Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted | Dale Morris, James Callister | 2004-09-28 |
| 6721875 | Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form | James E. McCormick, Jr., Donald Soltis | 2004-04-13 |
| 6711671 | Non-speculative instruction fetch in speculative processing | Donald Soltis | 2004-03-23 |
| 6678817 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine | Anuj Dua, James E. McCormick, Jr., Barry J. Arnold, Russell C. Brockmann, David Carl Kubicek +1 more | 2004-01-13 |
| 6647487 | Apparatus and method for shift register rate control of microprocessor instruction prefetches | James E. McCormick, Jr. | 2003-11-11 |
| 6629167 | Pipeline decoupling buffer for handling early data and late data | James E. McCormick, Jr. | 2003-09-30 |
| 6618801 | Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information | Patrick Knebel, Kevin Safford, Donald Soltis, Joel D. Lamb, Russell C. Brockmann | 2003-09-09 |
| 6516388 | Method and apparatus for reducing cache pollution | James E. McCormick, Jr. | 2003-02-04 |
| 6493792 | Mechanism for broadside reads of CAM structures | Terry L Lyon | 2002-12-10 |
| 5961655 | Opportunistic use of pre-corrected data to improve processor performance | Leith L. Johnson | 1999-10-05 |
| 5860097 | Associative cache memory with improved hit time | David Johnson | 1999-01-12 |
| 5860096 | Multi-level instruction cache for a computer | Patrick Knebel, Craig A. Gleason | 1999-01-12 |
| 5829049 | Simultaneous execution of two memory reference instructions with only one address calculation | William L. Walker, Mark R. Storey, Patrick Knebel | 1998-10-27 |
| 5751735 | Integrated debug trigger method and apparatus for an integrated circuit | Paul G. Tobin, Hosein Naaseh-Shahry | 1998-05-12 |