Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8533430 | Memory hashing for stride access | — | 2013-09-10 |
| 7788429 | Cross coupled unidirectional data ring | — | 2010-08-31 |
| 6920531 | Method and apparatus for updating and invalidating store data | — | 2005-07-19 |
| 6874077 | Parallel distributed function translation lookaside buffer | — | 2005-03-29 |
| 6874116 | Masking error detection/correction latency in multilevel cache transfers | Shawn Walker, Dean Mulla, Donald Soltis | 2005-03-29 |
| 6834327 | Multilevel cache system having unified cache tag memory | — | 2004-12-21 |
| 6772316 | Method and apparatus for updating and invalidating store data | — | 2004-08-03 |
| 6728823 | Cache connection with bypassing feature | Shawn Walker, Blaine Stackhouse | 2004-04-27 |
| 6704820 | Unified cache port consolidation | Shawn Walker, Dean Mulla | 2004-03-09 |
| 6625714 | Parallel distributed function translation lookaside buffer | — | 2003-09-23 |
| 6591393 | Masking error detection/correction latency in multilevel cache transfers | Shawn Walker, Dean Mulla, Donald Soltis | 2003-07-08 |
| 6557078 | Cache chain structure to implement high bandwidth low latency cache memory subsystem | Dean Mulla, Reid James Riedlinger, Thomas Grutkowski | 2003-04-29 |
| 6507892 | L1 cache memory | Dean Mulla, Reid James Riedlinger, Tom Grutkowski | 2003-01-14 |
| 6493812 | Apparatus and method for virtual address aliasing and multiple page size support in a computer system having a prevalidated cache | — | 2002-12-10 |
| 6493792 | Mechanism for broadside reads of CAM structures | Stephen R. Undy | 2002-12-10 |
| 6470437 | Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design | — | 2002-10-22 |
| 6427188 | Method and system for early tag accesses for lower-level caches in parallel with first-level cache | Eric Delano, Dean Mulla | 2002-07-30 |
| 5887183 | Method and system in a data processing system for loading and storing vectors in a plurality of modes | Ramesh Chandra Agarwal, Randall Dean Groves, Fred Gehrung Gustavson, Mark A. Johnson, Brett Olsson +1 more | 1999-03-23 |
| 5261071 | Dual pipe cache memory with out-of-order issue capability | — | 1993-11-09 |
| 5208838 | Clock signal multiplier | Dennis L. Wendell, Charles Hochstedler, Dan Lunecki | 1993-05-04 |
| 5153882 | Serial scan diagnostics apparatus and method for a memory device | Jeff Chritz | 1992-10-06 |
| 4660198 | Data capture logic for VLSI chips | — | 1987-04-21 |