Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11403194 | Systems and methods for in-field core failover | Eric J. Dehaemer, Arijit Biswas, Ian M. Steiner | 2022-08-02 |
| 10552270 | Systems and methods for in-field core failover | Eric J. Dehaemer, Arijit Biswas, Ian M. Steiner | 2020-02-04 |
| 9075614 | Managing power consumption in a multi-core processor | Eric Fetzer, Don Soltis, William J. Bowhill, Satish Shrimali, Krishnakanth V. Sistla +5 more | 2015-07-07 |
| 8423832 | System and method for preventing processor errors | Douglas J. Cutter, Rich McGowen, II | 2013-04-16 |
| 8020038 | System and method for adjusting operating points of a processor based on detected processor errors | Steven F. Liepe, Douglas J. Cutter | 2011-09-13 |
| 7698673 | Circuit and circuit design method | Steven Ray Afleck, Douglas Stirrett | 2010-04-13 |
| 7590509 | System and method for testing a processor | Douglas J. Cutter | 2009-09-15 |
| 7146457 | Content addressable memory selectively addressable in a physical address mode and a virtual address mode | Kuldeep Simha | 2006-12-05 |
| 6873565 | Dual-ported read SRAM cell with improved soft error immunity | Brandon Yelton, Steven Affleck | 2005-03-29 |
| 6647464 | System and method utilizing speculative cache access for improved performance | Dean Mulla, Tom Grutkowski | 2003-11-11 |
| 6583650 | Latching annihilation based logic gate | Samuel D. Naffziger, Jayen Desai | 2003-06-24 |
| 6557078 | Cache chain structure to implement high bandwidth low latency cache memory subsystem | Dean Mulla, Terry L Lyon, Thomas Grutkowski | 2003-04-29 |
| 6550034 | Built-in self test for content addressable memory | Donald R. Weiss | 2003-04-15 |
| 6539466 | System and method for TLB buddy entry self-timing | — | 2003-03-25 |
| 6539457 | Cache address conflict mechanism without store buffers | Dean Mulla, Thomas Grutkowski | 2003-03-25 |
| 6507892 | L1 cache memory | Dean Mulla, Terry L Lyon, Tom Grutkowski | 2003-01-14 |
| 6459304 | Latching annihilation based logic gate | Samuel D. Naffziger, Jayen Desai | 2002-10-01 |
| 6446187 | Virtual address bypassing using local page mask | Samuel D. Naffziger, Douglas J. Cutter, Christopher Seib | 2002-09-03 |
| 6427189 | Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline | Dean Mulla, Tom Grutkowski | 2002-07-30 |
| 6285579 | System and method for enabling/disabling SRAM banks for memory access | Donald R. Weiss | 2001-09-04 |
| 6226217 | Register structure with a dual-ended write mechanism | Donald R. Weiss | 2001-05-01 |
| 6208565 | Multi-ported register structure utilizing a pulse write mechanism | Donald R. Weiss | 2001-03-27 |
| 6192001 | Integrated weak write test mode (WWWTM) | Donald R. Weiss, John Wuu | 2001-02-20 |