| 12445120 |
Dynamic setup and hold times adjustment for memories |
Jaroslaw Kuszczak, Gaurav Rattan Singla |
2025-10-14 |
|
| 12414283 |
Devices and systems for flying bitline with jumper cell |
Sahilpreet Singh, Kerrie Vercant Underhill, Ricardo Cantu, Russell Schreiber |
2025-09-09 |
|
| 12346226 |
System and method for SEU detection and correction |
Kumar Rahul, Santosh Yachareni, Pierre Maillard, Mrinmoy Goswami, Tabrez Alam +3 more |
2025-07-01 |
|
| 12266585 |
Arrangement and thermal management of 3D stacked dies |
Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson |
2025-04-01 |
|
| 12212337 |
ECC optimization |
Kumar Rahul, Santosh Yachareni |
2025-01-28 |
|
| 12165700 |
SRAM power savings and write assist |
Russell Schreiber, Keith Kasprak |
2024-12-10 |
$237,856,000 |
| 12107076 |
Through-silicon via layout for multi-die integrated circuits |
Wonjun Jung, Jasmeet Singh Narang, Tyrone Tung Huang, Christopher Klement, Alan Dodson Smith +1 more |
2024-10-01 |
$299,271,000 |
| 12073919 |
Dual read port latch array bitcell |
Arijit Banerjee, Russell Schreiber |
2024-08-27 |
$259,969,000 |
| 12045469 |
Single event upset tolerant memory device |
Kumar Rahul, Santosh Yachareni, Nui Chong, Cheang-Whang Chang |
2024-07-23 |
|
| 12033721 |
Split read port latch array bit cell |
Arijit Banerjee, Russell Schreiber |
2024-07-09 |
$258,431,000 |
| 11869874 |
Stacked die circuit routing system and method |
David Johnson |
2024-01-09 |
$241,234,000 |
| 11822484 |
Low power cache |
Vydhyanathan Kalyanasundharam, Chintan S. Patel |
2023-11-21 |
$644,776,000 |
| 11804479 |
Scheme for enabling die reuse in 3D stacked products |
Milind S. Bhagavat, Brett P. Wilkerson, Rahul Agarwal |
2023-10-31 |
$171,949,000 |
| 11715514 |
Latch bit cells |
Russell Schreiber |
2023-08-01 |
$238,969,000 |
| 11710698 |
Dual-track bitline scheme for 6T SRAM cells |
Richard T. Schultz |
2023-07-25 |
$204,977,000 |
| 11676659 |
Memory with expandable row width |
Martin Paul Piorkowski |
2023-06-13 |
$166,732,000 |
| 11610627 |
Write masked latch bit cell |
Russell Schreiber |
2023-03-21 |
$410,108,000 |
| 11527270 |
Hybrid library latch array |
Russell Schreiber |
2022-12-13 |
$287,886,000 |
| 11437316 |
Folded cell layout for 6T SRAM cell |
Richard T. Schultz |
2022-09-06 |
$151,168,000 |
| 11233510 |
In memory logic functions using memory arrays |
Edward Chang |
2022-01-25 |
$180,690,000 |
| 11205477 |
Memory with expandable row width |
Martin Paul Piorkowski |
2021-12-21 |
$500,351,000 |
| 11189540 |
Arrangement and thermal management of 3D stacked dies |
Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson |
2021-11-30 |
$383,963,000 |
| 11164807 |
Arrangement and thermal management of 3D stacked dies |
Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson |
2021-11-02 |
$465,528,000 |
| 10839875 |
Timer for use dual voltage supplies |
Srinivas R. Sathu, Russell Schreiber, Martin Paul Piorkowski |
2020-11-17 |
$196,313,000 |
| 10783953 |
Memory with expandable row width |
Martin Paul Piorkowski |
2020-09-22 |
$76,515,000 |
