Issued Patents All Time
Showing 25 most recent of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414283 | Devices and systems for flying bitline with jumper cell | Sahilpreet Singh, Kerrie Vercant Underhill, Ricardo Cantu, Russell Schreiber | 2025-09-09 |
| 12346226 | System and method for SEU detection and correction | Kumar Rahul, Santosh Yachareni, Pierre Maillard, Mrinmoy Goswami, Tabrez Alam +3 more | 2025-07-01 |
| 12266585 | Arrangement and thermal management of 3D stacked dies | Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2025-04-01 |
| 12212337 | ECC optimization | Kumar Rahul, Santosh Yachareni | 2025-01-28 |
| 12165700 | SRAM power savings and write assist | Russell Schreiber, Keith Kasprak | 2024-12-10 |
| 12107076 | Through-silicon via layout for multi-die integrated circuits | Wonjun Jung, Jasmeet Singh Narang, Tyrone Tung Huang, Christopher Klement, Alan Dodson Smith +1 more | 2024-10-01 |
| 12073919 | Dual read port latch array bitcell | Arijit Banerjee, Russell Schreiber | 2024-08-27 |
| 12045469 | Single event upset tolerant memory device | Kumar Rahul, Santosh Yachareni, Nui Chong, Cheang-Whang Chang | 2024-07-23 |
| 12033721 | Split read port latch array bit cell | Arijit Banerjee, Russell Schreiber | 2024-07-09 |
| 11869874 | Stacked die circuit routing system and method | David Johnson | 2024-01-09 |
| 11822484 | Low power cache | Vydhyanathan Kalyanasundharam, Chintan S. Patel | 2023-11-21 |
| 11804479 | Scheme for enabling die reuse in 3D stacked products | Milind S. Bhagavat, Brett P. Wilkerson, Rahul Agarwal | 2023-10-31 |
| 11715514 | Latch bit cells | Russell Schreiber | 2023-08-01 |
| 11710698 | Dual-track bitline scheme for 6T SRAM cells | Richard T. Schultz | 2023-07-25 |
| 11676659 | Memory with expandable row width | Martin Paul Piorkowski | 2023-06-13 |
| 11610627 | Write masked latch bit cell | Russell Schreiber | 2023-03-21 |
| 11527270 | Hybrid library latch array | Russell Schreiber | 2022-12-13 |
| 11437316 | Folded cell layout for 6T SRAM cell | Richard T. Schultz | 2022-09-06 |
| 11233510 | In memory logic functions using memory arrays | Edward Chang | 2022-01-25 |
| 11205477 | Memory with expandable row width | Martin Paul Piorkowski | 2021-12-21 |
| 11189540 | Arrangement and thermal management of 3D stacked dies | Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2021-11-30 |
| 11164807 | Arrangement and thermal management of 3D stacked dies | Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2021-11-02 |
| 10839875 | Timer for use dual voltage supplies | Srinivas R. Sathu, Russell Schreiber, Martin Paul Piorkowski | 2020-11-17 |
| 10783953 | Memory with expandable row width | Martin Paul Piorkowski | 2020-09-22 |
| 10644826 | Flexibile interfaces using through-silicon via technology | Samuel D. Naffziger, Michael Kevin Ciraula, Russell Schreiber | 2020-05-05 |