Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509752 | Configuration of multi-die modules with through-silicon vias | Russell Schreiber, Michael Kevin Ciraula, Patrick J. Shyvers | 2019-12-17 |
| 10431517 | Arrangement and thermal management of 3D stacked dies | Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2019-10-01 |
| 10366734 | Programmable write word line boost for low voltage memory operation | Alexander W. Schaefer, Ravi Jotwani, Samiul Haque Khan, David Hugh McIntyre, Stephen V. Kosonocky +1 more | 2019-07-30 |
| 10311191 | Memory including side-car arrays with irregular sized entries | Patrick J. Shyvers, Ryan Alan Selby | 2019-06-04 |
| 10303398 | Swizzling in 3D stacked memory | Michael Kevin Ciraula, Russell Schreiber, Samuel D. Naffziger | 2019-05-28 |
| 10043572 | VSS bitcell sleep scheme involving modified bitcell for terminating sleep regions | Russell Schreiber, Keith Kasprak | 2018-08-07 |
| 9953687 | Pseudo-dynamic circuit for multi-voltage timing interlocks | Ryan T. Freese, Russell Schreiber | 2018-04-24 |
| 9575891 | Sidecar SRAM for high granularity in floor plan aspect ratio | John R. Riley, Russell Schreiber, Donald R. Weiss, William McGee | 2017-02-21 |
| 9355743 | Memory array test logic | Amlan Ghosh, Keith Kasprak, John R. Riley | 2016-05-31 |
| 9159409 | Method and apparatus for providing complimentary state retention | Donald R. Weiss | 2015-10-13 |
| 9053257 | Voltage-aware signal path synchronization | Russell Schreiber, Keith Kasprak | 2015-06-09 |
| 8958236 | Memory cell flipping for mitigating SRAM BTI | Keith Kasprak, Russell Schreiber | 2015-02-17 |
| 8464130 | Memory device and method thereof | Sang Hoo Dhong, Jin Cho, Gurupada Mandal | 2013-06-11 |
| 8276039 | Error detection device and methods thereof | Samuel D. Naffziger, Donald R. Weiss | 2012-09-25 |
| 7724567 | Memory device and method of refreshing | Sang Hoo Dhong, Jin Cho, Gurupada Mandal | 2010-05-25 |
| 7724578 | Sensing device for floating body cell memory and method thereof | Michael A. Dreesen, Donald R. Weiss | 2010-05-25 |
| 7430145 | System and method for avoiding attempts to access a defective portion of memory | Donald R. Weiss, Charles Morrganti | 2008-09-30 |
| 7133319 | Programmable weak write test mode (PWWTM) bias generation having logic high output default mode | Blaine Stackhouse, Donald R. Weiss | 2006-11-07 |
| 7076376 | System and method for calibrating weak write test mode (WWTM) | Donald R. Weiss, Richard L. Woodruff | 2006-07-11 |
| 6580635 | Bitline splitter | Todd W. Mellinger, Jonathan Lachman | 2003-06-17 |
| 6366526 | Static random access memory (SRAM) array central global decoder system and method | Samuel D. Naffziger, Donald R. Weiss | 2002-04-02 |
| 6282143 | Multi-port static random access memory design for column interleaved arrays | Kevin X. Zhang | 2001-08-28 |
| 6243287 | Distributed decode system and method for improving static random access memory (SRAM) density | Samuel D. Naffziger, Donald R. Weiss | 2001-06-05 |
| 6192001 | Integrated weak write test mode (WWWTM) | Donald R. Weiss, Reid James Riedlinger | 2001-02-20 |