Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424560 | Semiconductor chip device | Chia-Hao Cheng, Kong-Toon Ng, Rahul Agarwal | 2025-09-23 |
| 12374645 | Electronic device including dies and an interconnect coupled to the dies and processes of forming the same | Lei Fu, Raja Swaminathan | 2025-07-29 |
| 12278150 | Semiconductor package with annular package lid structure | Priyal Shah, Raja Swaminathan | 2025-04-15 |
| 12276850 | Fanout module integrating a photonic integrated circuit | Raja Swaminathan, Kong-Toon Ng, Rahul Agarwal | 2025-04-15 |
| 12266611 | Mixed density interconnect architectures using hybrid fan-out | Rahul Agarwal, Raja Swaminathan | 2025-04-01 |
| 12266585 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore | 2025-04-01 |
| 12249519 | Molded chip package with anchor structures | Priyal Shah, Milind S. Bhagavat, Lei Fu, Rahul Agarwal | 2025-03-11 |
| 12165981 | 3D semiconductor package with die-mounted voltage regulator | Gabriel H. Loh, Raja Swaminathan, Rahul Agarwal | 2024-12-10 |
| 12107075 | Hybrid bonded interconnect bridging | Lei Fu, Rahul Agarwal | 2024-10-01 |
| 11911839 | Low temperature hybrid bonding | Priyal Shah, Rahul Agarwal, Raja Swaminathan | 2024-02-27 |
| 11855061 | Offset-aligned three-dimensional integrated circuit | Milind S. Bhagavat, Rahul Agarwal, Dmitri Yudanov | 2023-12-26 |
| 11804479 | Scheme for enabling die reuse in 3D stacked products | John Wuu, Milind S. Bhagavat, Rahul Agarwal | 2023-10-31 |
| 11742301 | Fan-out package with reinforcing rivets | Rahul Agarwal, Milind S. Bhagavat, Priyal Shah, Chia-Hao Cheng, Lei Fu | 2023-08-29 |
| 11709327 | Fanout module integrating a photonic integrated circuit | Raja Swaminathan, Kong-Toon Ng, Rahul Agarwal | 2023-07-25 |
| 11676940 | Hybrid bonded interconnect bridging | Lei Fu, Rahul Agarwal | 2023-06-13 |
| 11437359 | Offset-aligned three-dimensional integrated circuit | Milind S. Bhagavat, Rahul Agarwal, Dmitri Yudanov | 2022-09-06 |
| 11367628 | Molded chip package with anchor structures | Priyal Shah, Milind S. Bhagavat, Lei Fu, Rahul Agarwal | 2022-06-21 |
| 11189540 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore | 2021-11-30 |
| 11164807 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore | 2021-11-02 |
| 10573630 | Offset-aligned three-dimensional integrated circuit | Milind S. Bhagavat, Rahul Agarwal, Dmitri Yudanov | 2020-02-25 |
| 10431517 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore | 2019-10-01 |
| 10312221 | Stacked dies and dummy components for improved thermal performance | Rahul Agarwal, Kaushik Mysore Srinivasa Setty, Milind S. Bhagavat | 2019-06-04 |
| 9324667 | Semiconductor devices with compliant interconnects | Trent S. Uehling, Lawrence S. Klingbeil, Jr., Mostafa Vadipour, Leo M. Higgins, III | 2016-04-26 |
| 8766453 | Packaged integrated circuit having large solder pads and method for forming | Trent S. Uehling | 2014-07-01 |
| 8704370 | Semiconductor package structure having an air gap and method for forming | Trent S. Uehling, Burton J. Carpenter | 2014-04-22 |