Issued Patents All Time
Showing 1–25 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430136 | Systems and methods for branch misprediction aware cache prefetcher training | Jagadish B. Kotra, John Kalamatianos | 2025-09-30 |
| 12373361 | Systems, methods, and devices for advanced memory technology | Niti Madan, James R. Magro | 2025-07-29 |
| 12360907 | Region pattern-matching hardware prefetcher | Marko Scrbak, Akhil Arunkumar, John Kalamatianos | 2025-07-15 |
| 12353338 | Locality-based data processing | — | 2025-07-08 |
| 12332824 | Backside interface for chiplet architecture mixing | Todd David Basso | 2025-06-17 |
| 12299445 | Register based SIMD lookup table operations | Yasuko Eckert, Bradford M. Beckmann, Michael Estlick, Jay Fleischman | 2025-05-13 |
| 12248516 | Flexible, scalable graph-processing accelerator | Ganesh Suryanarayan Dasika, Michael Ignatowski, Michael Schulte, Valentina Salapura, Angela Beth Dalton | 2025-03-11 |
| 12217059 | Systems and methods for programmed branch predictors | Alexander Toufic Freij, Onur Kayiran | 2025-02-04 |
| 12165981 | 3D semiconductor package with die-mounted voltage regulator | Raja Swaminathan, Rahul Agarwal, Brett P. Wilkerson | 2024-12-10 |
| 12153524 | Apparatus, system, and method for throttling prefetchers to prevent training on irregular memory accesses | John Kalamatianos, Marko Scrbak, Akhil Arunkumar | 2024-11-26 |
| 11922107 | Quantum circuit mapping for multi-programmed quantum computers | Anthony Gutierrez, Salonik Resch, Yasuko Eckert, Mark H. Oskin, Vedula Venkata Srikant Bharadwaj | 2024-03-05 |
| 11921784 | Flexible, scalable graph-processing accelerator | Ganesh Suryanarayan Dasika, Michael Ignatowski, Michael Schulte, Valentina Salapura, Angela Beth Dalton | 2024-03-05 |
| 11847062 | Re-fetching data for L3 cache data evictions into a last-level cache | Tarun Nakra, Jay Fleischman, Gautam Tarasingh Hazari, Akhil Arunkumar, William L. Walker +2 more | 2023-12-19 |
| 11830817 | Creating interconnects between dies using a cross-over die and through-die vias | Rahul Agarwal, Raja Swaminathan, Michael Alfano, Alan D. Smith, Gabriel Wong +1 more | 2023-11-28 |
| 11775799 | Runtime extension for neural network training with heterogeneous memory | Georgios Mappouras, Amin Farmahini-Farahani, Sudhanva Gurumurthi, Abhinav Vishnu | 2023-10-03 |
| 11640840 | Victim row refreshes for memories in electronic devices | SeyedMohammad SeyedzadehDelcheh | 2023-05-02 |
| 11550728 | System and method for page table caching memory | Derrick Allen Aguren, Eric Van Tassell, Jay Fleischman | 2023-01-10 |
| 11507519 | Data compression and encryption based on translation lookaside buffer evictions | Jagadish B. Kotra, Matthew R. Poremba | 2022-11-22 |
| 11494300 | Page table walker with page table entry (PTE) physical address prediction | — | 2022-11-08 |
| 11475305 | Activation function functional block for electronic devices | — | 2022-10-18 |
| 11403221 | Memory access response merging in a memory hierarchy | Onur Kayiran, Yasuko Eckert, Mark H. Oskin, Steven Raasch, Maxim V. Kazakov | 2022-08-02 |
| 11360891 | Adaptive cache reconfiguration via clustering | Mohamed Assem Abd ElMohsen Ibrahim, Onur Kayiran, Yasuko Eckert | 2022-06-14 |
| 11342933 | Lossy significance compression with lossy restoration | — | 2022-05-24 |
| 11275829 | Mechanism for throttling untrusted interconnect agents | Maurice B. Steinman | 2022-03-15 |
| 11232039 | Cache for storing regions of data | — | 2022-01-25 |