Issued Patents All Time
Showing 51–75 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10078588 | Using leases for entries in a translation lookaside buffer | Arkaprava Basu, Mark H. Oskin, Andrew G. Kegel, David S. Christie, Kevin J. McGrath | 2018-09-18 |
| 10055359 | Pinning objects in multi-level memory hierarchies | Sergey Blagodurov, John R. Slice | 2018-08-21 |
| 10049044 | Asynchronous cache flushing | Michael W. Boyer, Nuwan Jayasena | 2018-08-14 |
| 9990289 | System and method for repurposing dead cache blocks | Derek Robert Hower, Shuai Che | 2018-06-05 |
| 9971700 | Cache with address space mapping to slice subsets | — | 2018-05-15 |
| 9916265 | Traffic rate control for inter-class data migration in a multiclass memory system | Sergey Blagodurov, Yasuko Eckert | 2018-03-13 |
| 9910605 | Page migration in a hybrid memory device | Nuwan Jayasena, James M. O'Connor, Niladrish Chatterjee | 2018-03-06 |
| 9825843 | Die-stacked device with partitioned multi-hop network | Mithuna S. Thottethodi | 2017-11-21 |
| 9818455 | Query operations for stacked-die memory device | Nuwan Jayasena, James M. O'Connor, Yasuko Eckert | 2017-11-14 |
| 9804996 | Computation memory operations in a logic layer of a stacked memory | James M. O'Connor, Nuwan Jayasena, Michael Ignatowski, Michael Schulte | 2017-10-31 |
| 9792961 | Distributed computing with phase change material thermal management | Manish Arora, Nuwan Jayasena, Michael Schulte, Srilatha Manne | 2017-10-17 |
| 9766936 | Selecting a resource from a set of resources for performing an operation | Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu +1 more | 2017-09-19 |
| 9755964 | Multi-protocol header generation system | David A. Roberts, Michael Ignatowski, Nuwan Jayasena | 2017-09-05 |
| 9753858 | DRAM cache with tags and data jointly stored in physical rows | Mark D. Hill | 2017-09-05 |
| 9727241 | Memory page access detection | David A. Roberts, Mitesh R. Meswani, Mark Richard Nutter, John R. Slice, Prashant Jayaprakash Nair +1 more | 2017-08-08 |
| 9697147 | Stacked memory device with metadata management | James M. O'Connor, Bradford M. Beckmann, Michael Ignatowski | 2017-07-04 |
| 9672161 | Configuring a cache management mechanism based on future accesses in a cache | Yasuko Eckert | 2017-06-06 |
| 9552294 | Dynamically configuring regions of a main memory in a write-back mode or a write-through mode | Jaewoong Sim, Mithuna S. Thottethodi | 2017-01-24 |
| 9535831 | Page migration in a 3D stacked hybrid memory | Nuwan Jayasena, James M. O'Connor, Niladrish Chatterjee | 2017-01-03 |
| 9529718 | Batching modified blocks to the same dram page | Syed Ali Jafri, Yasuko Eckert, Srilatha Manne, Mithuna S. Thottethodi | 2016-12-27 |
| 9489321 | Scheduling memory accesses using an efficient row burst value | James M. O'Connor, Niladrish Chatterjee, Nuwan Jayasena | 2016-11-08 |
| 9477605 | Memory hierarchy using row-based compression | James M. O'Connor | 2016-10-25 |
| 9454419 | Partitionable data bus | Yi Xu, James M. O'Connor | 2016-09-27 |
| 9405703 | Translation lookaside buffer | — | 2016-08-02 |
| 9406403 | Spare memory external to protected memory | Vilas Sridharan, James M. O'Connor | 2016-08-02 |