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USPTO Patent Rankings Data through Dec 31, 2025
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Arkaprava Basu — 19 Patents

AMD: 17 patents #669 of 9,280Top 8%
WARF: 2 patents #1,011 of 4,123Top 25%
Overall (All Time): #229,345 of 4,157,543Top 6%
19 Patents All Time
Arkaprava Basu has been granted 19 US patents while listed as an inventor at AMD. The first was granted in 2014 and the most recent in September 2025. Arkaprava Basu ranks #229,345 of 4,157,543 US inventors in our database (top 5.5%). Patent records list Arkaprava Basu in Kanchinakote, WI, IN.

Issued Patents All Time

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12411711 Enforcing central processing unit quality of service guarantees when servicing accelerator requests Joseph L. Greathouse 2025-09-09
11573724 Scoped persistence barriers for non-volatile memories Mitesh R. Meswani, Dibakar Gope, Sooraj Puthoor 2023-02-07 $236,799,000
11275613 Enforcing central processing unit quality of service guarantees when servicing accelerator requests Joseph L. Greathouse 2022-03-15 $138,395,000
11144473 Quality of service for input/output memory management unit Michael W. LeBeane, Eric Van Tassell 2021-10-12 $183,562,000
11140107 System and method of managing electronic meeting invitations Andrew G. Kegel 2021-10-05 $210,291,000
10592279 Multi-processor apparatus and method of detection and acceleration of lagging tasks Dmitri Yudanov, David A. Roberts, Mitesh R. Meswani, Sergey Blagodurov 2020-03-17 $27,927,000
10552339 Dynamically adapting mechanism for translation lookaside buffer shootdowns Joseph L. Greathouse 2020-02-04 $60,710,000
10503658 Page migration with varying granularity Jee Ho Ryoo 2019-12-10 $38,861,000
10437736 Single instruction multiple data page table walk scheduling at input output memory management unit Eric Van Tassell, Mark H. Oskin, Guilherme Cox, Gabriel H. Loh 2019-10-08 $23,319,000
10324650 Scoped persistence barriers for non-volatile memories Mitesh R. Meswani, Dibakar Gope, Sooraj Puthoor 2019-06-18 $31,887,000
10282292 Cluster-based migration in a multi-level memory hierarchy Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh 2019-05-07 $22,156,000
10261916 Adaptive extension of leases for entries in a translation lookaside buffer Amro Awad, Sergey Blagodurov, Mark H. Oskin, Gabriel H. Loh, Andrew G. Kegel +2 more 2019-04-16 $37,439,000
10078588 Using leases for entries in a translation lookaside buffer Mark H. Oskin, Gabriel H. Loh, Andrew G. Kegel, David S. Christie, Kevin J. McGrath 2018-09-18 $23,108,000
10019283 Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread Dmitri Yudanov, Sergey Blagodurov, Sooraj Puthoor, Joseph L. Greathouse 2018-07-10 $11,440,000
10019377 Managing cache coherence using information in a page table Bradford M. Beckmann, Shuai Che, Sooraj Puthoor 2018-07-10 $11,440,000
9983655 Method and apparatus for performing inter-lane power management Mitesh R. Meswani, David A. Roberts, Dmitri Yudanov, Sergey Blagodurov 2018-05-29 $23,774,000
9547603 I/O memory management unit providing self invalidated mapping Mark D. Hill, Michael M. Swift 2017-01-17
9158704 Virtual memory management system with reduced latency Mark D. Hill, Michael M. Swift 2015-10-13
8812786 Dual-granularity state tracking for directory-based cache coherence Bradfod M. Beckmann, Steven K. Reinhardt 2014-08-19 $3,461,000