Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411711 | Enforcing central processing unit quality of service guarantees when servicing accelerator requests | Joseph L. Greathouse | 2025-09-09 |
| 11573724 | Scoped persistence barriers for non-volatile memories | Mitesh R. Meswani, Dibakar Gope, Sooraj Puthoor | 2023-02-07 |
| 11275613 | Enforcing central processing unit quality of service guarantees when servicing accelerator requests | Joseph L. Greathouse | 2022-03-15 |
| 11144473 | Quality of service for input/output memory management unit | Michael W. LeBeane, Eric Van Tassell | 2021-10-12 |
| 11140107 | System and method of managing electronic meeting invitations | Andrew G. Kegel | 2021-10-05 |
| 10592279 | Multi-processor apparatus and method of detection and acceleration of lagging tasks | Dmitri Yudanov, David A. Roberts, Mitesh R. Meswani, Sergey Blagodurov | 2020-03-17 |
| 10552339 | Dynamically adapting mechanism for translation lookaside buffer shootdowns | Joseph L. Greathouse | 2020-02-04 |
| 10503658 | Page migration with varying granularity | Jee Ho Ryoo | 2019-12-10 |
| 10437736 | Single instruction multiple data page table walk scheduling at input output memory management unit | Eric Van Tassell, Mark H. Oskin, Guilherme Cox, Gabriel H. Loh | 2019-10-08 |
| 10324650 | Scoped persistence barriers for non-volatile memories | Mitesh R. Meswani, Dibakar Gope, Sooraj Puthoor | 2019-06-18 |
| 10282292 | Cluster-based migration in a multi-level memory hierarchy | Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh | 2019-05-07 |
| 10261916 | Adaptive extension of leases for entries in a translation lookaside buffer | Amro Awad, Sergey Blagodurov, Mark H. Oskin, Gabriel H. Loh, Andrew G. Kegel +2 more | 2019-04-16 |
| 10078588 | Using leases for entries in a translation lookaside buffer | Mark H. Oskin, Gabriel H. Loh, Andrew G. Kegel, David S. Christie, Kevin J. McGrath | 2018-09-18 |
| 10019283 | Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread | Dmitri Yudanov, Sergey Blagodurov, Sooraj Puthoor, Joseph L. Greathouse | 2018-07-10 |
| 10019377 | Managing cache coherence using information in a page table | Bradford M. Beckmann, Shuai Che, Sooraj Puthoor | 2018-07-10 |
| 9983655 | Method and apparatus for performing inter-lane power management | Mitesh R. Meswani, David A. Roberts, Dmitri Yudanov, Sergey Blagodurov | 2018-05-29 |
| 9547603 | I/O memory management unit providing self invalidated mapping | Mark D. Hill, Michael M. Swift | 2017-01-17 |
| 9158704 | Virtual memory management system with reduced latency | Mark D. Hill, Michael M. Swift | 2015-10-13 |
| 8812786 | Dual-granularity state tracking for directory-based cache coherence | Bradfod M. Beckmann, Steven K. Reinhardt | 2014-08-19 |