Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411711 | Enforcing central processing unit quality of service guarantees when servicing accelerator requests | Arkaprava Basu | 2025-09-09 |
| 12277020 | Default boost mode state for devices | Adam Neil Calder Clark, Stephen Kushnir | 2025-04-15 |
| 12033238 | Register compaction with early release | Brian D. Emberling, Anthony Gutierrez | 2024-07-09 |
| 11995351 | DMA engines configured to perform first portion data transfer commands with a first DMA engine and second portion data transfer commands with second DMA engine | Sean Keely, Alan Dodson Smith, Anthony Asaro, Ling Wang, Milind N. Nemlekar +2 more | 2024-05-28 |
| 11972261 | Hardware device for enforcing atomicity for memory operations | Vydhyanathan Kalyanasundharam, Shyam Sekhar | 2024-04-30 |
| 11853734 | Compiler-initiated tile replacement to enable hardware acceleration resources | Gregory P. Rodgers | 2023-12-26 |
| 11687251 | Dynamic repartition of memory physical address mapping | Alan Dodson Smith, Francisco L. Duran, Felix Kuehling, Anthony Asaro | 2023-06-27 |
| 11669473 | Allreduce enhanced direct memory access functionality | Abhinav Vishnu | 2023-06-06 |
| 11663001 | Family of lossy sparse load SIMD instructions | Sanchari Sen, Derrick Allen Aguren | 2023-05-30 |
| 11604737 | Dynamic modification of coherent atomic memory operations | Steven Tony Tye, Mark Fowler, Milind N. Nemlekar | 2023-03-14 |
| 11556250 | Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs | Jagadish B. Kotra, Karthik Rao | 2023-01-17 |
| 11556162 | Per-instruction energy debugging using instruction sampling hardware | Shijia Wei, John Kalamatianos | 2023-01-17 |
| 11347486 | Compiler-initiated tile replacement to enable hardware acceleration resources | Gregory P. Rodgers | 2022-05-31 |
| 11275613 | Enforcing central processing unit quality of service guarantees when servicing accelerator requests | Arkaprava Basu | 2022-03-15 |
| 11137809 | Runtime localized cooling of high-performance processors | Karthik Rao, Wei Huang, Xudong An, Manish Arora | 2021-10-05 |
| 10936697 | Optimized and scalable sparse triangular linear systems on networks of accelerators | Khaled Hamidouche, Michael W. LeBeane, Nicholas Malaya | 2021-03-02 |
| 10928789 | Distributed multi-input multi-output control theoretic method to manage heterogeneous systems | Raghavendra Pradyumna Pothukuchi, Leonardo Piga | 2021-02-23 |
| 10725670 | Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs | Jagadish B. Kotra, Karthik Rao | 2020-07-28 |
| 10713059 | Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units | Mitesh R. Meswani, Sooraj Puthoor, Dmitri Yudanov, James M. O'Connor | 2020-07-14 |
| 10691772 | High-performance sparse triangular solve on graphics processing units | — | 2020-06-23 |
| 10552339 | Dynamically adapting mechanism for translation lookaside buffer shootdowns | Arkaprava Basu | 2020-02-04 |
| 10067710 | Detecting buffer overflows in general-purpose GPU applications | Christopher D. Erb, Michael G. Collins | 2018-09-04 |
| 10019283 | Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread | Dmitri Yudanov, Sergey Blagodurov, Arkaprava Basu, Sooraj Puthoor | 2018-07-10 |
| 9990203 | Hardware accuracy counters for application precision and quality feedback | Leonardo de Paula Rosa Piga, Abhinandan Majumdar, Indrani Paul, Wei-Ming Huang, Manish Arora | 2018-06-05 |
| 9697176 | Efficient sparse matrix-vector multiplication on parallel processors | Mayank Daga | 2017-07-04 |