Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430136 | Systems and methods for branch misprediction aware cache prefetcher training | Gabriel H. Loh, John Kalamatianos | 2025-09-30 |
| 12387767 | Method and apparatus for quantization and dequantization of neural network input and output data using processing-in-memory | Ioannis Papadopoulos, Vignesh Adhinarayanan, Ashwin Aji | 2025-08-12 |
| 12373207 | Implementing a micro-operation cache with compaction | John Kalamatianos | 2025-07-29 |
| 12339783 | Managing a cache using per memory region reuse distance estimation | John Kalamatianos, Asmita Pal | 2025-06-24 |
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | John Kalamatianos, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan, Patrick J. Shyvers +1 more | 2025-05-20 |
| 12287739 | Accessing a cache based on an address translation buffer result | John Kalamatianos | 2025-04-29 |
| 12265470 | Bypassing cache directory lookups for processing-in-memory instructions | Travis Henry Boraten, David Andrew Werner | 2025-04-01 |
| 12197378 | Method and apparatus to expedite system services using processing-in-memory (PIM) | Kishore Punniyamurthy | 2025-01-14 |
| 12189953 | Speculative dram request enabling and disabling | John Kalamatianos | 2025-01-07 |
| 12153926 | Processor-guided execution of offloaded instructions using fixed function operations | John Kalamatianos, Michael T. Clark, Marius Evers, William L. Walker, Paul James Moyer +1 more | 2024-11-26 |
| 12147338 | Leveraging processing in memory registers as victim buffers | Dong Wang | 2024-11-19 |
| 12099723 | Tag and data configuration for fine-grained cache memory | Marko Scrbak | 2024-09-24 |
| 12073251 | Offloading computations from a processor to remote execution logic | Nagadastagiri Reddy Challapalle, John Kalamatianos | 2024-08-27 |
| 12050531 | Data compression and decompression for processing in memory | Kishore Punniyamurthy | 2024-07-30 |
| 12019547 | Dispatch bandwidth of memory-centric requests by bypassing storage array address checking | John Kalamatianos, Gagandeep Panwar | 2024-06-25 |
| 12019566 | Arbitrating atomic memory operations | Sergey Blagodurov, Johnathan Alsop, Marko Scrbak, Ganesh S. Dasika | 2024-06-25 |
| 11960404 | Method and apparatus for reducing the latency of long latency memory requests | John Kalamatianos | 2024-04-16 |
| 11921634 | Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host | John Kalamatianos, Yasuko Eckert, Yonghae Kim | 2024-03-05 |
| 11880312 | Data as compute | Kishore Punniyamurthy, SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov, Ganesh S. Dasika | 2024-01-23 |
| 11868777 | Processor-guided execution of offloaded instructions using fixed function operations | John Kalamatianos, Michael T. Clark, Marius Evers, William L. Walker, Paul James Moyer +1 more | 2024-01-09 |
| 11797201 | Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems | Mahzabeen Islam, Shaizeen Aga, Nuwan Jayasena | 2023-10-24 |
| 11762777 | Method and apparatus for a dram cache tag prefetcher | Marko Scrbak, Matthew R. Poremba | 2023-09-19 |
| 11756606 | Method and apparatus for recovering regular access performance in fine-grained DRAM | Sriseshan Srikanth, Vignesh Adhinarayanan, Sergey Blagodurov | 2023-09-12 |
| 11726783 | Filtering micro-operations for a micro-operation cache in a processor | Marko Scrbak, Mahzabeen Islam, John Kalamatianos | 2023-08-15 |
| 11721384 | Hardware-assisted dynamic random access memory (DRAM) row merging | — | 2023-08-08 |