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USPTO Patent Rankings Data through Dec 31, 2025
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Marius Evers — 32 Patents

AMD: 30 patents #324 of 9,280Top 4%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Santa Clara, CA: #448 of 9,301 inventorsTop 5%
California: #15,919 of 386,348 inventorsTop 5%
Overall (All Time): #110,428 of 4,157,543Top 3%
32 Patents All Time
Marius Evers has been granted 32 US patents while listed as an inventor at AMD. The first was granted in 2007 and the most recent in October 2025. Marius Evers ranks #110,428 of 4,157,543 US inventors in our database (top 2.7%). Patent records list Marius Evers in Santa Clara, CA, US.

Issued Patents All Time

Showing 1–25 of 32 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12443702 Protection against branch target buffer poisoning by a management layer David A. Kaplan 2025-10-14
12204908 Storing incidental branch predictions to reduce latency of misprediction recovery Douglas R. Williams, Ashok Tirupathy Venkatachar, Sudherssen Kalaiselvan 2025-01-21
12153926 Processor-guided execution of offloaded instructions using fixed function operations John Kalamatianos, Michael T. Clark, William L. Walker, Paul James Moyer, Jay Fleischman +1 more 2024-11-26 $172,029,000
12153927 Merged branch target buffer entries Thomas Clouqueur, Aparna Mandke, Steven R. Havlir, Robert B. Cohen, Anthony Jarvis 2024-11-26 $172,029,000
11868777 Processor-guided execution of offloaded instructions using fixed function operations John Kalamatianos, Michael T. Clark, William L. Walker, Paul James Moyer, Jay Fleischman +1 more 2024-01-09 $241,234,000
11797665 Protection against branch target buffer poisoning by a management layer David A. Kaplan 2023-10-24 $302,839,000
11734011 Context partitioning of branch prediction structures David A. Kaplan 2023-08-22 $334,921,000
11704248 Retaining cache entries of a processor core during a powered-down state William L. Walker, Michael L. Golden 2023-07-18 $179,194,000
11620224 Instruction cache prefetch throttle Aparna Thyagarajan, Ashok Tirupathy Venkatachar, Angelo Wong, William E. Jones 2023-04-04 $295,108,000
11416256 Selectively performing ahead branch prediction based on types of branch instructions Aparna Thyagarajan, Ashok Tirupathy Venkatachar 2022-08-16 $209,744,000
11334384 Scheduler queue assignment burst mode Alok Garg, Scott Andrew McLelland, Matthew T. Sobel 2022-05-17 $824,569,000
11256505 Using loop exit prediction to accelerate or suppress loop mode of a processor Arunachalam Annamalai, Aparna Thyagarajan, Anthony Jarvis 2022-02-22 $613,861,000
11055098 Branch target buffer with early return prediction Aparna Thyagarajan, Arunachalam Annamalai 2021-07-06 $185,003,000
11048506 Tracking stores and loads by bypassing load store units Krishnan V. Ramani, Kai Troester, Frank C. Galloway, David N. Suggs, Michael Achenbach +1 more 2021-06-29 $580,413,000
10956157 Taint protection during speculative execution David A. Kaplan 2021-03-23 $85,424,000
10956332 Retaining cache entries of a processor core during a powered-down state William L. Walker, Michael L. Golden 2021-03-23 $85,424,000
10949201 Processor with accelerated lock instruction operation Scott Thomas Bingham, Krishnan V. Ramani, Thomas Kunjan 2021-03-16 $264,077,000
10929141 Selective use of taint protection during speculative execution David A. Kaplan 2021-02-23 $188,100,000
10915322 Using loop exit prediction to accelerate or suppress loop mode of a processor Arunachalam Annamalai, Aparna Thyagarajan, Anthony Jarvis 2021-02-09 $253,203,000
10896044 Low latency synchronization for operation cache and instruction cache fetching and decoding instructions Dhanaraj Bapurao Tavare, Ashok Tirupathy Venkatachar, Arunachalam Annamalai, Donald A. Priore, Douglas R. Williams 2021-01-19 $176,337,000
10768937 Using return address predictor to speed up control stack return address verification David A. Kaplan, Debjit Das Sarma 2020-09-08 $79,748,000
10732979 Selectively performing ahead branch prediction based on types of branch instructions Aparna Thyagarajan, Ashok Tirupathy Venkatachar 2020-08-04 $140,893,000
10671535 Stride prefetching across memory pages John Kalamatianos, Paul Keltcher, Chitresh Narasimhaiah 2020-06-02 $45,689,000
10127044 Bandwidth increase in branch prediction unit and level 1 instruction cache Douglas R. Williams, Sahil Arora, Nikhil Gupta, Wei-Yu Chen, Debjit Das Sarma 2018-11-13 $39,610,000
9916243 Method and apparatus for performing a bus lock and translation lookaside buffer invalidation William L. Walker, Paul James Moyer, Richard Martin Born, Eric Christopher Morton, David S. Christie +1 more 2018-03-13 $10,106,000