Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204908 | Storing incidental branch predictions to reduce latency of misprediction recovery | Douglas R. Williams, Ashok Tirupathy Venkatachar, Sudherssen Kalaiselvan | 2025-01-21 |
| 12153926 | Processor-guided execution of offloaded instructions using fixed function operations | John Kalamatianos, Michael T. Clark, William L. Walker, Paul James Moyer, Jay Fleischman +1 more | 2024-11-26 |
| 12153927 | Merged branch target buffer entries | Thomas Clouqueur, Aparna Mandke, Steven R. Havlir, Robert B. Cohen, Anthony Jarvis | 2024-11-26 |
| 11868777 | Processor-guided execution of offloaded instructions using fixed function operations | John Kalamatianos, Michael T. Clark, William L. Walker, Paul James Moyer, Jay Fleischman +1 more | 2024-01-09 |
| 11797665 | Protection against branch target buffer poisoning by a management layer | David A. Kaplan | 2023-10-24 |
| 11734011 | Context partitioning of branch prediction structures | David A. Kaplan | 2023-08-22 |
| 11704248 | Retaining cache entries of a processor core during a powered-down state | William L. Walker, Michael L. Golden | 2023-07-18 |
| 11620224 | Instruction cache prefetch throttle | Aparna Thyagarajan, Ashok Tirupathy Venkatachar, Angelo Wong, William E. Jones | 2023-04-04 |
| 11416256 | Selectively performing ahead branch prediction based on types of branch instructions | Aparna Thyagarajan, Ashok Tirupathy Venkatachar | 2022-08-16 |
| 11334384 | Scheduler queue assignment burst mode | Alok Garg, Scott Andrew McLelland, Matthew T. Sobel | 2022-05-17 |
| 11256505 | Using loop exit prediction to accelerate or suppress loop mode of a processor | Arunachalam Annamalai, Aparna Thyagarajan, Anthony Jarvis | 2022-02-22 |
| 11055098 | Branch target buffer with early return prediction | Aparna Thyagarajan, Arunachalam Annamalai | 2021-07-06 |
| 11048506 | Tracking stores and loads by bypassing load store units | Krishnan V. Ramani, Kai Troester, Frank C. Galloway, David N. Suggs, Michael Achenbach +1 more | 2021-06-29 |
| 10956157 | Taint protection during speculative execution | David A. Kaplan | 2021-03-23 |
| 10956332 | Retaining cache entries of a processor core during a powered-down state | William L. Walker, Michael L. Golden | 2021-03-23 |
| 10949201 | Processor with accelerated lock instruction operation | Scott Thomas Bingham, Krishnan V. Ramani, Thomas Kunjan | 2021-03-16 |
| 10929141 | Selective use of taint protection during speculative execution | David A. Kaplan | 2021-02-23 |
| 10915322 | Using loop exit prediction to accelerate or suppress loop mode of a processor | Arunachalam Annamalai, Aparna Thyagarajan, Anthony Jarvis | 2021-02-09 |
| 10896044 | Low latency synchronization for operation cache and instruction cache fetching and decoding instructions | Dhanaraj Bapurao Tavare, Ashok Tirupathy Venkatachar, Arunachalam Annamalai, Donald A. Priore, Douglas R. Williams | 2021-01-19 |
| 10768937 | Using return address predictor to speed up control stack return address verification | David A. Kaplan, Debjit Das Sarma | 2020-09-08 |
| 10732979 | Selectively performing ahead branch prediction based on types of branch instructions | Aparna Thyagarajan, Ashok Tirupathy Venkatachar | 2020-08-04 |
| 10671535 | Stride prefetching across memory pages | John Kalamatianos, Paul Keltcher, Chitresh Narasimhaiah | 2020-06-02 |
| 10127044 | Bandwidth increase in branch prediction unit and level 1 instruction cache | Douglas R. Williams, Sahil Arora, Nikhil Gupta, Wei-Yu Chen, Debjit Das Sarma | 2018-11-13 |
| 9916243 | Method and apparatus for performing a bus lock and translation lookaside buffer invalidation | William L. Walker, Paul James Moyer, Richard Martin Born, Eric Christopher Morton, David S. Christie +1 more | 2018-03-13 |
| 9697146 | Resource management for northbridge using tokens | Douglas R. Williams, Vydhyanathan Kalyanasundharam, Michael K. Fertig | 2017-07-04 |