RC

Robert B. Cohen

AM AMD: 5 patents #2,159 of 9,279Top 25%
Motorola: 4 patents #2,599 of 12,470Top 25%
Micron: 3 patents #3,077 of 6,345Top 50%
NL Ncipher Corporation Limited: 1 patents #10 of 20Top 50%
Overall (All Time): #331,025 of 4,157,543Top 8%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12222797 Dynamic configuration of processor sub-components James A. Mossman, Sudherssen Kalaiselvan, Tzu-Wei Lin 2025-02-11
12153927 Merged branch target buffer entries Thomas Clouqueur, Marius Evers, Aparna Mandke, Steven R. Havlir, Anthony Jarvis 2024-11-26
12039337 Processor with multiple fetch and decode pipelines Tzu-Wei Lin, Anthony J. Bybell, Bill Kai Chiu Kwan, Frank C. Galloway 2024-07-16
11907126 Processor with multiple op cache pipelines Tzu-Wei Lin, Anthony J. Bybell, Sudherssen Kalaiselvan, James A. Mossman 2024-02-20
11579884 Instruction address translation and caching for primary and alternate branch prediction paths Ashok Tirupathy Venkatachar, Steven R. Havlir 2023-02-14
7913261 Application-specific information-processing method, system, and apparatus Oscar Mitchell, Eleanor Coy, Rajat Datta, Randall Findley, James Garrett +4 more 2011-03-22
6950911 Multi-port memory device with multiple modes of operation and improved expansion characteristics Jeff Ladwig 2005-09-27
6625699 Multi-port memory device with multiple modes of operation and improved expansion characteristics Jeff Ladwig 2003-09-23
6418489 Direct memory access controller and method therefor Kristen L. Mason, Gary R. Morrison, Jeffrey M. Polega, Donald L. Tietjen, Frank C. Galloway +2 more 2002-07-09
6233659 Multi-port memory device with multiple modes of operation and improved expansion characteristics Jeff Ladwig 2001-05-15
5220526 Method and apparatus for indicating a duplication of entries in a content addressable storage device Grady L. Giles, Yui K. Ho 1993-06-15
5115506 Method and apparatus for preventing recursion jeopardy Robert E. Garner 1992-05-19
5048214 Revolver grip with cartridge storage 1991-09-17
4727485 Paged memory management unit which locks translators in translation cache if lock specified in translation table William M. Keshlear 1988-02-23