GG

Grady L. Giles

Motorola: 10 patents #938 of 12,470Top 8%
AM AMD: 5 patents #2,159 of 9,279Top 25%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
🗺 Texas: #9,006 of 125,132 inventorsTop 8%
Overall (All Time): #289,919 of 4,157,543Top 7%
16
Patents All Time

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
12100464 Repairable latch array Joel Thornton Irby 2024-09-24
11657892 Repairable latch array Joel Thornton Irby 2023-05-23
9194914 Power supply monitor for detecting faults during scan testing Stephen V. Kosonocky 2015-11-24
9046574 Test circuit having scan warm-up James A. Wingfield, Atchyuth K. Gorti 2015-06-02
8103924 Test access mechanism for multi-core processor or other integrated circuit Brian N. Hoang, Timothy J. Wood 2012-01-24
7925937 Apparatus for testing embedded memory read paths Joel Thornton Irby, Alexander W. Schaefer, Gregory A. Constant, Floyd L. Dankert, Amy M. Novak 2011-04-12
6272588 Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry Thomas K. Johnston, William Daune Atwell 2001-08-07
6167484 Method and apparatus for leveraging history bits to optimize memory refresh performance John Mark Boyer, William C. Bruce, Jr., Thomas K. Johnston, Bernard J. Pappert, John J. Vaglica 2000-12-26
6085334 Method and apparatus for testing an integrated memory device Kerry Ken Kanbe, William C. Bruce, Jr. 2000-07-04
5889788 Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation Matthew D. Pressly, Alfred L. Crouch 1999-03-30
5812561 Scan based testing of an integrated circuit for compliance with timing specifications Alfred L. Crouch, Odis Dale Amason, Jr., Matthew D. Pressly, Clark Gilson Shepard, Michael Alan Mateja +3 more 1998-09-22
5774476 Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit Matthew D. Pressly 1998-06-30
5369752 Method and apparatus for shifting data in an array of storage elements in a data processing system William Daune Atwell, Jesse R. Wilson, Richard B. Reis 1994-11-29
5220526 Method and apparatus for indicating a duplication of entries in a content addressable storage device Yui K. Ho, Robert B. Cohen 1993-06-15
5015875 Toggle-free scan flip-flop Jesse R. Wilson 1991-05-14
4680760 Accelerated test apparatus and support logic for a content addressable memory Jesse R. Wilson, Terry V. Hulett 1987-07-14