| 5889788 |
Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation |
Grady L. Giles, Alfred L. Crouch |
1999-03-30 |
| 5812561 |
Scan based testing of an integrated circuit for compliance with timing specifications |
Grady L. Giles, Alfred L. Crouch, Odis Dale Amason, Jr., Clark Gilson Shepard, Michael Alan Mateja +3 more |
1998-09-22 |
| 5774476 |
Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit |
Grady L. Giles |
1998-06-30 |
| 5717700 |
Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing |
Alfred L. Crouch, Bernard J. Pappert |
1998-02-10 |
| 5617531 |
Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor |
Alfred L. Crouch, James G. Gay, Clark Gilson Shepard, Pamela S. Laakso |
1997-04-01 |
| 5592493 |
Serial scan chain architecture for a data processing system and method of operation |
Alfred L. Crouch, Joseph C. Circello, Richard Duerden |
1997-01-07 |
| 5383143 |
Self re-seeding linear feedback shift register (LFSR) data processing system for generating a pseudo-random test bit stream and method of operation |
Alfred L. Crouch |
1995-01-17 |
