Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12210618 | Method and system for insertion of cybersecurity and hardware assurance instruments within intergrated circuits and electronic systems using multi-stage hardware marking | Peter Lawrence Levin, John David Akin, Adam Wade Ley, Matthew McKinnon Ritonia, Wesley Layton Ellington +1 more | 2025-01-28 |
| 12026250 | Method, system, and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems in relation to hardware trojans | Peter Lawrence Levin | 2024-07-02 |
| 11736501 | Method, system, and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems using machine learning instruments and machine learning analysis | Peter Lawrence Levin, John David Akin, Adam Wade Ley, Matthew McKinnon Ritonia, Wesley Layton Ellington +1 more | 2023-08-22 |
| 11693052 | Using embedded time-varying code generator to provide secure access to embedded content in an on-chip access architecture | James M. Johnson | 2023-07-04 |
| 11681795 | Method, system and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems in relation to hardware trojans | Eve Naomi Hunter, Peter Lawrence Levin | 2023-06-20 |
| 11333706 | Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture | James M. Johnson | 2022-05-17 |
| 11277419 | Method, system, and apparatus for verification of operation using GPS receiver input within integrated circuits and electronic systems using an operation navigation system | Peter Lawrence Levin, John David Akin, Adam Wade Ley, Matthew McKinnon Ritonia, Wesley Layton Ellington +1 more | 2022-03-15 |
| 11157619 | Method and system for selection of location for placement of trojans, triggers and instruments within integrated circuits and electronic systems using contributory operation analysis | — | 2021-10-26 |
| 10909284 | Method and system for selection of location for placement of trojans, triggers and instruments within integrated circuits and electronic systems using weighted controllability and observability analysis | — | 2021-02-02 |
| 10690718 | Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture | James M. Johnson | 2020-06-23 |
| 9811690 | Protecting hidden content in integrated circuits | Jennifer Lynn Dworak, Adam Zygmontowicz, John C. Potter | 2017-11-07 |
| 9305186 | Protection of proprietary embedded instruments | John C. Potter | 2016-04-05 |
| 8881301 | Protection of proprietary embedded instruments | John C. Potter | 2014-11-04 |
| 8615691 | Process for improving design-limited yield by localizing potential faults from production test data | Richard C. Dokken, Gerald Chan, John C. Potter | 2013-12-24 |
| 8060851 | Method for operating a secure semiconductor IP server to support failure analysis | Richard C. Dokken, Gerald Chan, Jacob J Orbon | 2011-11-15 |
| 8010856 | Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains | Stephen A. Cannon, Richard C. Dokken, Gary A. Winblad | 2011-08-30 |
| 7853846 | Locating hold time violations in scan chains by generating patterns on ATE | Stephen A. Cannon, Richard C. Dokken, Gary A. Winblad | 2010-12-14 |
| 7348796 | Method and system for network-on-chip and other integrated circuit architectures | Peter Lawrence Levin, Paul Bradley | 2008-03-25 |
| 6701476 | Test access mechanism for supporting a configurable built-in self-test circuit and method thereof | Bahram Pouya, Gregory Dean Young, Jeffrey L. Freeman | 2004-03-02 |
| 6598192 | Method and apparatus for testing an integrated circuit | Teresa Louise McLaurin, Donald L. Tietjen, Kristen L. Mason | 2003-07-22 |
| 5995731 | Multiple BIST controllers for testing multiple embedded memory arrays | Jennifer L. McKeown, Clark Gilson Shepard | 1999-11-30 |
| 5929650 | Method and apparatus for performing operative testing on an integrated circuit | Bernard J. Pappert, Clark Gilson Shepard, Robert M. Ash | 1999-07-27 |
| 5889788 | Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation | Matthew D. Pressly, Grady L. Giles | 1999-03-30 |
| 5812561 | Scan based testing of an integrated circuit for compliance with timing specifications | Grady L. Giles, Odis Dale Amason, Jr., Matthew D. Pressly, Clark Gilson Shepard, Michael Alan Mateja +3 more | 1998-09-22 |
| 5719878 | Scannable storage cell and method of operation | Ruey J. Yu | 1998-02-17 |