RD

Richard C. Dokken

VP Verigy (Singapore) Pte.: 4 patents #11 of 115Top 10%
AP Advantest (Singapore) Pte: 2 patents #5 of 43Top 15%
IN Inovys: 2 patents #4 of 8Top 50%
📍 San Ramon, CA: #552 of 2,140 inventorsTop 30%
🗺 California: #73,997 of 386,348 inventorsTop 20%
Overall (All Time): #652,297 of 4,157,543Top 20%
8
Patents All Time

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
8615691 Process for improving design-limited yield by localizing potential faults from production test data Gerald Chan, John C. Potter, Alfred L. Crouch 2013-12-24
8453026 Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures Gerald Chan 2013-05-28
8060851 Method for operating a secure semiconductor IP server to support failure analysis Gerald Chan, Jacob J Orbon, Alfred L. Crouch 2011-11-15
8010856 Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains Stephen A. Cannon, Alfred L. Crouch, Gary A. Winblad 2011-08-30
8006149 System and method for device performance characterization in physical and logical domains with AC SCAN testing Gerald Chan, Phillip D. Burlison 2011-08-23
7853846 Locating hold time violations in scan chains by generating patterns on ATE Stephen A. Cannon, Alfred L. Crouch, Gary A. Winblad 2010-12-14
7568139 Process for identifying the location of a break in a scan chain in real time Gerald Chan, Takehiko Ishii 2009-07-28
7047463 Method and system for automatically determining a testing order when executing a test flow Donald V. Organ 2006-05-16