Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7581151 | Method and apparatus for affecting a portion of an integrated circuit | William C. Moyer | 2009-08-25 |
| 7185251 | Method and apparatus for affecting a portion of an integrated circuit | William C. Moyer | 2007-02-27 |
| 6832280 | Data processing system having an adaptive priority controller | Afzal M. Malik, William C. Moyer | 2004-12-14 |
| 6167484 | Method and apparatus for leveraging history bits to optimize memory refresh performance | John Mark Boyer, Grady L. Giles, Thomas K. Johnston, Bernard J. Pappert, John J. Vaglica | 2000-12-26 |
| 6085334 | Method and apparatus for testing an integrated memory device | Grady L. Giles, Kerry Ken Kanbe | 2000-07-04 |
| 5912562 | Quiescent current monitor circuit for wafer level integrated circuit testing | Bernard J. Pappert | 1999-06-15 |
| 5646949 | Method and apparatus for generating instructions for use in testing a microprocessor | Wai-on Law, Elizabeth M. Rudnick, Judith E. K. Laurens | 1997-07-08 |
| 5517637 | Method for testing a test architecture within a circuit | Joseph E. Drufke, Jr., Chema O. Eluwa, John M. Hudson | 1996-05-14 |
| 5347523 | Data processing system having serial self address decoding and method of operation | Sunil Khatri, William C. Moyer | 1994-09-13 |
| 4980888 | Memory testing system | Donald W. Smelser | 1990-12-25 |
| 4679194 | Load double test instruction | Tulley M. Peters | 1987-07-07 |
| 4409653 | Method of performing a clear and wait operation with a single instruction | — | 1983-10-11 |
| 4380798 | Semaphore register including ownership bits | Paul D. Shannon | 1983-04-19 |
| 4344133 | Method for synchronizing hardware and software | Fuad H. Musa, Terry F. Ritter | 1982-08-10 |