Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6077306 | Bus interface slicing mechanism allowing for a control/data path slice | Jeffrey A. Metzger, Nitin D. Godiwala, Barry A. Maskas, Kurt M. Thaller, Paul M. Goodwin +1 more | 2000-06-20 |
| 5956352 | Adjustable filter for error detecting and correcting system | David A. Tatosian, Paul M. Goodwin | 1999-09-21 |
| 5918029 | Bus interface slicing mechanism allowing for a control/data-path slice | Jeffrey A. Metzger, Nitin D. Godiwala, Barry A. Maskas, Kurt M. Thaller, Paul M. Goodwin +1 more | 1999-06-29 |
| 5754753 | Multiple-bit error correction in computer main memory | — | 1998-05-19 |
| 5659713 | Memory stream buffer with variable-size prefetch depending on memory interleaving configuration | Paul M. Goodwin, David A. Tatosian | 1997-08-19 |
| 5490113 | Memory stream buffer | David A. Tatosian, Paul M. Goodwin, Kurt M. Thaller | 1996-02-06 |
| 5481555 | System and method for error detection and reducing simultaneous switching noise | Paul Wade, Samuel H. Duncan | 1996-01-02 |
| 5461718 | System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory | David A. Tatosian, Paul M. Goodwin | 1995-10-24 |
| 5459742 | Solid state disk memory using storage devices with defects | Charles F. Cassidy, Paul Kemp | 1995-10-17 |
| 5452418 | Method of using stream buffer to perform operation under normal operation mode and selectively switching to test mode to check data integrity during system operation | David A. Tatosian, Paul M. Goodwin | 1995-09-19 |
| 5392288 | Addressing technique for a fault tolerant block-structured storage device | Richard Rudman, Paul Kemp | 1995-02-21 |
| 5371870 | Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching | Paul M. Goodwin, David A. Tatosian | 1994-12-06 |
| 5357529 | Error detecting and correcting apparatus and method with transparent test mode | David A. Tatosian, Paul M. Goodwin | 1994-10-18 |
| 5276809 | Method and apparatus for capturing real-time data bus cycles in a data processing system | Lawrence A. P. Chisvin, John K. Grooms, Richard L. Sites | 1994-01-04 |
| 5251310 | Method and apparatus for exchanging blocks of information between a cache memory and a main memory | Nicholas Warchol, Gary P. Lidington | 1993-10-05 |
| 5216672 | Parallel diagnostic mode for testing computer memory | David A. Tatosian, Paul M. Goodwin | 1993-06-01 |
| 5191404 | High density memory array packaging | Andrew L. Wu, E. William Bruce, II, John O'Dea | 1993-03-02 |
| 5099484 | Multiple bit error detection and correction system employing a modified Reed-Solomon code incorporating address parity and catastrophic failure detection | — | 1992-03-24 |
| 5033048 | Memory selftest method and apparatus same | Donald C. Pierce, Edward Howard Utzig, Robert Norman Crouse, Noreen Hession, Hansel A. Collins | 1991-07-16 |
| 5014273 | Bad data algorithm | Michael A. Gagliardo, Paul M. Goodwin | 1991-05-07 |
| 4980888 | Memory testing system | William C. Bruce, Jr. | 1990-12-25 |
| 4817095 | Byte write error code method and apparatus | James C. Stegeman, Lawrence A. P. Chisvin | 1989-03-28 |
| 4782487 | Memory test method and apparatus | — | 1988-11-01 |