Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6077306 | Bus interface slicing mechanism allowing for a control/data path slice | Nitin D. Godiwala, Barry A. Maskas, Kurt M. Thaller, Paul M. Goodwin, Donald W. Smelser +1 more | 2000-06-20 |
| 5918029 | Bus interface slicing mechanism allowing for a control/data-path slice | Nitin D. Godiwala, Barry A. Maskas, Kurt M. Thaller, Paul M. Goodwin, Donald W. Smelser +1 more | 1999-06-29 |
| 5629950 | Fault management scheme for a cache memory | Nitin D. Godiwala, Kurt M. Thaller, Barry A. Maskas | 1997-05-13 |
| 5553266 | Update vs. invalidate policy for a snoopy bus protocol | Barry A. Maskas | 1996-09-03 |
| 5361267 | Scheme for error handling in a computer system | Nitin D. Godiwala, Barry A. Maskas, Kurt M. Thaller | 1994-11-01 |
| 5319766 | Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system | Kurt M. Thaller, Nitin D. Godiwala, Barry A. Maskas | 1994-06-07 |
| 5297107 | Interconnect arrangement for electronic components disposed on a circuit board | Paul J. Graffam | 1994-03-22 |
| 5287517 | Self-compensating voltage level shifting circuit | Barry A. Maskas, George J. Harris | 1994-02-15 |