KT

Kurt M. Thaller

DE Digital Equipment: 14 patents #34 of 2,100Top 2%
CC Compaq Computer: 2 patents #518 of 1,604Top 35%
SB Stratus Technologies Bermuda: 1 patents #22 of 49Top 45%
📍 Acton, MA: #157 of 1,334 inventorsTop 15%
🗺 Massachusetts: #6,946 of 88,656 inventorsTop 8%
Overall (All Time): #279,769 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDate
6718474 Methods and apparatus for clock management based on environmental conditions Jeffrey Somers, Nicholas Warchol 2004-04-06
6091608 Method and apparatus for simplified and compact component addition to a printed circuit board Eugene Smith 2000-07-18
6077306 Bus interface slicing mechanism allowing for a control/data path slice Jeffrey A. Metzger, Nitin D. Godiwala, Barry A. Maskas, Paul M. Goodwin, Donald W. Smelser +1 more 2000-06-20
5918029 Bus interface slicing mechanism allowing for a control/data-path slice Jeffrey A. Metzger, Nitin D. Godiwala, Barry A. Maskas, Paul M. Goodwin, Donald W. Smelser +1 more 1999-06-29
5890281 Method for simplified and compact component addition to a printed circuit board Eugene Smith 1999-04-06
5629950 Fault management scheme for a cache memory Nitin D. Godiwala, Jeffrey A. Metzger, Barry A. Maskas 1997-05-13
5594875 Method and apparatus to provide pended transaction on a non-pended system bus 1997-01-14
5586294 Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer Paul M. Goodwin 1996-12-17
5555382 Intelligent snoopy bus arbiter Nitin D. Godiwala, Barry A. Maskas 1996-09-10
5553258 Method and apparatus for forming an exchange address for a system with different size caches Nitin D. Godiwala, Barry A. Maskas 1996-09-03
5490113 Memory stream buffer David A. Tatosian, Paul M. Goodwin, Donald W. Smelser 1996-02-06
5388247 History buffer control to reduce unnecessary allocations in a memory stream buffer Paul M. Goodwin, Barry A. Maskas 1995-02-07
5361267 Scheme for error handling in a computer system Nitin D. Godiwala, Barry A. Maskas, Jeffrey A. Metzger 1994-11-01
5319766 Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system Jeffrey A. Metzger, Nitin D. Godiwala, Barry A. Maskas 1994-06-07
5319785 Polling of I/O device status comparison performed in the polled I/O device 1994-06-07
5305354 Aborting synchronizer Nitin D. Godiwala 1994-04-19
5274628 Multisignal synchronizer with shared last stage Nitin D. Godiwala 1993-12-28