Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9838471 | Method and an apparatus for work request arbitration in a network processor | Wilson P. Snyder, II, Richard E. Kessler, Daniel Dever, David William Kravitz | 2017-12-05 |
| 9811467 | Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor | Wilson P. Snyder, II, Richard E. Kessler, Daniel Dever | 2017-11-07 |
| 7773617 | System and method for arbitration for virtual channels to prevent livelock in a richly-connected multi-processor computer system | Judson S. Leonard, Matthew Reilly | 2010-08-10 |
| 7773618 | System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels | Judson S. Leonard, Matthew Reilly | 2010-08-10 |
| 7773616 | System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel | Matthew Reilly, Judson S. Leonard | 2010-08-10 |
| 7689856 | Mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multi-processor computing system | — | 2010-03-30 |
| 7295557 | System and method for scheduling message transmission and processing in a digital data network | Shawn Adam Clayton, David R. Follett, Maria Clara Gutierrez, David Wells, James B. Williams | 2007-11-13 |
| 7283471 | System and method for regulating message flow in a digital data network | Maria Clara Gutierrez, Shawn Adam Clayton, David R. Follett, Harold E. Roman, Richard F. Prohaska +1 more | 2007-10-16 |
| 6795442 | System and method for scheduling message transmission and processing in a digital data network | Shawn Adam Clayton, David R. Follett, Maria Clara Gutierrez, David Wells, James B. Williams | 2004-09-21 |
| 6791948 | Distributed switch and connection control arrangement and method for digital communications network | Peter J. Desnoyers, Shawn Adam Clayton | 2004-09-14 |
| 6570850 | System and method for regulating message flow in a digital data network | Maria Clara Gutierrez, Shawn Adam Clayton, David R. Follett, Richard F. Prohaska, Harold E. Roman +1 more | 2003-05-27 |
| 6077306 | Bus interface slicing mechanism allowing for a control/data path slice | Jeffrey A. Metzger, Barry A. Maskas, Kurt M. Thaller, Paul M. Goodwin, Donald W. Smelser +1 more | 2000-06-20 |
| 5918029 | Bus interface slicing mechanism allowing for a control/data-path slice | Jeffrey A. Metzger, Barry A. Maskas, Kurt M. Thaller, Paul M. Goodwin, Donald W. Smelser +1 more | 1999-06-29 |
| 5712858 | Test methodology for exceeding tester pin count for an asic device | Andrew Myer Ebert, Chester Pawlowski | 1998-01-27 |
| 5629950 | Fault management scheme for a cache memory | Kurt M. Thaller, Jeffrey A. Metzger, Barry A. Maskas | 1997-05-13 |
| 5555382 | Intelligent snoopy bus arbiter | Kurt M. Thaller, Barry A. Maskas | 1996-09-10 |
| 5553258 | Method and apparatus for forming an exchange address for a system with different size caches | Kurt M. Thaller, Barry A. Maskas | 1996-09-03 |
| 5361267 | Scheme for error handling in a computer system | Barry A. Maskas, Kurt M. Thaller, Jeffrey A. Metzger | 1994-11-01 |
| 5319766 | Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system | Kurt M. Thaller, Jeffrey A. Metzger, Barry A. Maskas | 1994-06-07 |
| 5305354 | Aborting synchronizer | Kurt M. Thaller | 1994-04-19 |
| 5274628 | Multisignal synchronizer with shared last stage | Kurt M. Thaller | 1993-12-28 |