Anthony Jarvis — 21 Patents at AMD

Anthony Jarvis has been granted 21 US patents while listed as an inventor at AMD. The first was granted in 2004 and the most recent in April 2025. Anthony Jarvis ranks #201,324 of 4,157,543 US inventors in our database (top 4.8%). Patent records list Anthony Jarvis in Boxborough, MA, US.

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Showing 1–21 of 21 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12282776	Hybrid parallelized tagged geometric (TAGE) branch prediction	Thomas Clouqueur	2025-04-22
12153927	Merged branch target buffer entries	Thomas Clouqueur, Marius Evers, Aparna Mandke, Steven R. Havlir, Robert B. Cohen	2024-11-26	$172,029,000
11416253	Multiple-table branch target buffer	Thomas Clouqueur	2022-08-16	$209,744,000
11256505	Using loop exit prediction to accelerate or suppress loop mode of a processor	Arunachalam Annamalai, Marius Evers, Aparna Thyagarajan	2022-02-22	$613,861,000
11216279	Loop exit predictor	Thomas Clouqueur	2022-01-04	$290,378,000
10915322	Using loop exit prediction to accelerate or suppress loop mode of a processor	Arunachalam Annamalai, Marius Evers, Aparna Thyagarajan	2021-02-09	$253,203,000
10713054	Multiple-table branch target buffer	Thomas Cloqueur	2020-07-14	$34,730,000
10635591	Systems and methods for selectively filtering, buffering, and processing cache coherency probes	Ashok Tirupathy Venkatachar	2020-04-28	$42,649,000
9778934	Power efficient pattern history table fetch in branch predictor	James David Dundas	2017-10-03	$10,070,000
8788797	Combined level 1 and level 2 branch predictor	Trivikram Krishnamurthy	2014-07-22	$2,511,000
8667257	Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit	Ravindra N. Bhargava, David N. Suggs	2014-03-04	$1,501,000
8578141	Loop predictor and method for instruction fetching using a loop predictor	—	2013-11-05	$2,151,000
8181005	Hybrid branch prediction device with sparse and dense prediction caches	Gerald D. Zuraski, Jr., James David Dundas	2012-05-15	$7,029,000
7757066	System and method for executing variable latency load operations in a date processor	Paolo Faraboschi	2010-07-13
7143268	Circuit and method for instruction compression and dispersal in wide-issue processors	Paolo Faraboschi, Mark Owen Homewood, Geoffrey M. Brown, Gary L. Vondran, Jr.	2006-11-28
7093107	Bypass circuitry for use in a pipelined processor	—	2006-08-15	$8,540,000
7028164	Instruction fetch apparatus for wide issue processors and method of operation	Mark Owen Homewood, Gary L. Vondran, Jr.	2006-04-11	$8,313,000
6922773	System and method for encoding constant operands in a wide issue processor	Paolo Faraboschi, Alexander J. Starr, Geoffrey M. Brown, Mark Owen Homewood, Gary L. Vondran, Jr.	2005-07-26
6865665	Processor pipeline cache miss apparatus and method for operation	—	2005-03-08	$6,410,000
6807628	System and method for supporting precise exceptions in a data processor having a clustered architecture	Mark Owen Homewood, Alexander J. Starr	2004-10-19	$8,675,000
6772355	System and method for reducing power consumption in a data processor having a clustered architecture	Mark Owen Homewood	2004-08-03	$7,606,000

Anthony Jarvis — 21 Patents

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