Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11256505 | Using loop exit prediction to accelerate or suppress loop mode of a processor | Marius Evers, Aparna Thyagarajan, Anthony Jarvis | 2022-02-22 |
| 11055098 | Branch target buffer with early return prediction | Aparna Thyagarajan, Marius Evers | 2021-07-06 |
| 10915322 | Using loop exit prediction to accelerate or suppress loop mode of a processor | Marius Evers, Aparna Thyagarajan, Anthony Jarvis | 2021-02-09 |
| 10896044 | Low latency synchronization for operation cache and instruction cache fetching and decoding instructions | Marius Evers, Dhanaraj Bapurao Tavare, Ashok Tirupathy Venkatachar, Donald A. Priore, Douglas R. Williams | 2021-01-19 |