Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11294678 | Scheduler queue assignment | Matthew T. Sobel, Alok Garg | 2022-04-05 |
| 10896044 | Low latency synchronization for operation cache and instruction cache fetching and decoding instructions | Marius Evers, Dhanaraj Bapurao Tavare, Ashok Tirupathy Venkatachar, Arunachalam Annamalai, Douglas R. Williams | 2021-01-19 |
| 9300293 | Fault detection for a distributed signal line | John G. Petrovick, Jr., Stephen V. Kosonocky, Robert S. Orefice | 2016-03-29 |
| 8656339 | Method for analyzing sensitivity and failure probability of a circuit | Kevin M. Gillespie, Timothy J. Correia | 2014-02-18 |
| 8589661 | Odd and even start bit vectors | Mike Butler, Steven Beigelmacher | 2013-11-19 |
| 7933760 | Bitcell simulation device and methods | Russell Schreiber, Keith Kasprak | 2011-04-26 |
| 7647472 | High speed and high throughput digital communications processor with efficient cooperation between programmable processing components | Thomas B. Brightman, Andrew D. Funk, David J. Husak, Edward J. McLellan, Andrew Brown +4 more | 2010-01-12 |
| 7100020 | Digital communications processor | Thomas B. Brightman, Andrew Brown, John F. Brown, James Arthur Farrell, Andrew D. Funk +4 more | 2006-08-29 |
| 6807186 | Architectures for a single-stage grooming switch | William J. Dally, John H. Edmondson, Ephrem C. Wu, John W. Poulton | 2004-10-19 |
| 6408401 | Embedded RAM with self-test and self-repair with spare rows and columns | Dilip K. Bhavsar | 2002-06-18 |
| 6076176 | Encoding of failing bit addresses to facilitate multi-bit failure detect using a wired-OR scheme | Dilip K. Bhavsar, Tina P. Zou | 2000-06-13 |