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Timing verifier for MOS devices and related method |
Nevine Nassif, Madhav Desai, Harry Ray Fair, III, Roy Badeau, Nicholas Lee Rethman |
2005-04-05 |
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Method for compacting an instruction queue |
Timothy C. Fischer, Daniel Leibholz, Bruce Gieseke |
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Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list |
Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Daniel Leibholz, Derrick R. Meyer |
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Nevine Nassif, Dale Hayward Hall, Gill Watt |
2003-12-02 |
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Method and circuits for early detection of a full queue |
Timothy C. Fischer, Daniel Leibholz |
2003-04-01 |
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Timing verifier for MOS devices and related method |
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Harry Ray Fair, III, Nevine Nassif, Gill Watt |
2002-08-20 |
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Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list |
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2002-06-11 |
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Bruce Gieseke |
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| 6167508 |
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Bruce Gieseke |
2000-12-26 |
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