James Arthur Farrell — 16 Patents at Compaq Computer

James Arthur Farrell has been granted 16 US patents while listed as an inventor at Compaq Computer. The first was granted in 1991 and the most recent in January 2012. James Arthur Farrell ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list James Arthur Farrell in Marlboro, MA, US.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8090930	Method and circuits for early detection of a full queue	Timothy C. Fischer, Daniel Leibholz	2012-01-03	$14,988,000
7647472	High speed and high throughput digital communications processor with efficient cooperation between programmable processing components	Thomas B. Brightman, Andrew D. Funk, David J. Husak, Edward J. McLellan, Andrew Brown +4 more	2010-01-12
7100020	Digital communications processor	Thomas B. Brightman, Andrew Brown, John F. Brown, Andrew D. Funk, David J. Husak +4 more	2006-08-29
6877142	Timing verifier for MOS devices and related method	Nevine Nassif, Madhav Desai, Harry Ray Fair, III, Roy Badeau, Nicholas Lee Rethman	2005-04-05	$15,181,000
6704856	Method for compacting an instruction queue	Timothy C. Fischer, Daniel Leibholz, Bruce Gieseke	2004-03-09	$13,217,000
6675288	Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list	Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Daniel Leibholz, Derrick R. Meyer	2004-01-06	$15,903,000
6658506	Method and apparatus for performing timing verification of a circuit	Nevine Nassif, Dale Hayward Hall, Gill Watt	2003-12-02
6542987	Method and circuits for early detection of a full queue	Timothy C. Fischer, Daniel Leibholz	2003-04-01	$12,265,000
6473888	Timing verifier for MOS devices and related method	Nevine Nassif, Madhav Desai, Harry Ray Fair, III, Roy Badeau, Nicholas Lee Rethman	2002-10-29
6438732	Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)	Harry Ray Fair, III, Nevine Nassif, Gill Watt	2002-08-20
6405304	Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list	Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Daniel Leibholz, Derrick R. Meyer	2002-06-11	$14,396,000
6249855	Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle	Bruce Gieseke	2001-06-19	$27,502,000
6167508	Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency	Bruce Gieseke	2000-12-26	$40,926,000
6122728	Technique for ordering internal processor register accesses	Daniel Leibholz, Sharon Marie Britton, Timothy C. Fischer	2000-09-19	$51,516,000
6098166	Speculative issue of instructions under a load miss shadow	Daniel Leibholz, Sven Meier, Timothy C. Fischer, Derrick R. Meyer	2000-08-01	$44,998,000
5014195	Configurable set associative cache with decoded data element enable lines	Richard L. Sites	1991-05-07	$10,723,000

James Arthur Farrell — 16 Patents

Issued Patents All Time

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