Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE46474 | Multiple write during simultaneous memory access of a multi-port memory device | Hui Hui Ngu | 2017-07-11 |
| 8848479 | Multiple write during simultaneous memory access of a multi-port memory device | Hui Hui Ngu | 2014-09-30 |
| 7062850 | Method of forming electrical interconnects having electromigration-inhibiting segments to a critical length | Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement | 2006-06-20 |
| 6904675 | Method of forming electrical interconnects having electromigration-inhibiting plugs | Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement | 2005-06-14 |
| 6807107 | Semiconductor memory with shadow memory cell | William McGee, Ognjen Milic-Strkalj | 2004-10-19 |
| 6798712 | Wordline latching in semiconductor memories | William McGee, Ognjen Milic-Strkalj | 2004-09-28 |
| 6704856 | Method for compacting an instruction queue | James Arthur Farrell, Timothy C. Fischer, Daniel Leibholz | 2004-03-09 |
| 6678951 | Method of forming electrical interconnects having electromigration-inhibiting plugs | Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement | 2004-01-20 |
| 6675288 | Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Harry Ray Fair, III, Daniel Leibholz, Derrick R. Meyer | 2004-01-06 |
| 6433389 | Silicon on insulator logic circuit utilizing diode switching elements | — | 2002-08-13 |
| 6405304 | Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Harry Ray Fair, III, Daniel Leibholz, Derrick R. Meyer | 2002-06-11 |
| 6363471 | Mechanism for handling 16-bit addressing in a processor | Stephan G. Meier, William McGee, Ramsey W. Haddad | 2002-03-26 |
| 6249855 | Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle | James Arthur Farrell | 2001-06-19 |
| 6245996 | Electrical interconnect structure having electromigration-inhibiting segments | Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement | 2001-06-12 |
| 6195377 | Embedded input logic in a high input impedance strobed CMOS differential sense amplifier | Shane Bell | 2001-02-27 |
| 6167508 | Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency | James Arthur Farrell | 2000-12-26 |
| 5890201 | Content addressable memory having memory cells storing don't care states for address translation | Edward J. McLellan | 1999-03-30 |
| 5784709 | Translating buffer and method for translating addresses utilizing invalid and don't care states | Edward J. McLellan | 1998-07-21 |
| 5568415 | Content addressable memory having a pair of memory cells storing don't care states for address translation | Edward J. McLellan | 1996-10-22 |
| 5023480 | Push-pull cascode logic | Robert A. Conrad, James J. Montanaro, Daniel W. Dobberpuhl | 1991-06-11 |