Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8850278 | Fault tolerant scannable glitch latch | Kevin M. Gillespie, Joseph Siegel, Dwight K. Elvey | 2014-09-30 |
| 7206916 | Partial address compares stored in translation lookaside buffer | Michael Estlick, David R. Akeson | 2007-04-17 |
| 6877142 | Timing verifier for MOS devices and related method | Nevine Nassif, Madhav Desai, James Arthur Farrell, Roy Badeau, Nicholas Lee Rethman | 2005-04-05 |
| 6794902 | Virtual ground circuit | Matthew Becker, Marc Lamere, Jonathan A. White | 2004-09-21 |
| 6675288 | Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Bruce Gieseke, Daniel Leibholz, Derrick R. Meyer | 2004-01-06 |
| 6473888 | Timing verifier for MOS devices and related method | Nevine Nassif, Madhav Desai, James Arthur Farrell, Roy Badeau, Nicholas Lee Rethman | 2002-10-29 |
| 6438732 | Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL) | James Arthur Farrell, Nevine Nassif, Gill Watt | 2002-08-20 |
| 6405304 | Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Bruce Gieseke, Daniel Leibholz, Derrick R. Meyer | 2002-06-11 |