Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7260797 | Method and apparatus for estimating parasitic capacitance | Shabbir H. Batterywala, Narendra V. Shenoy | 2007-08-21 |
| 6877142 | Timing verifier for MOS devices and related method | Nevine Nassif, James Arthur Farrell, Harry Ray Fair, III, Roy Badeau, Nicholas Lee Rethman | 2005-04-05 |
| 6606587 | Method and apparatus for estimating elmore delays within circuit designs | Nevine Nassif, Dale Hayward Hall | 2003-08-12 |
| 6473888 | Timing verifier for MOS devices and related method | Nevine Nassif, James Arthur Farrell, Harry Ray Fair, III, Roy Badeau, Nicholas Lee Rethman | 2002-10-29 |