Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12333309 | Differential pipeline delays in a coprocessor | Jay Fleischman, Michael Sedmak, Erik Swanson, Sneha V. Desai | 2025-06-17 |
| 12299445 | Register based SIMD lookup table operations | Gabriel H. Loh, Yasuko Eckert, Bradford M. Beckmann, Jay Fleischman | 2025-05-13 |
| 12229563 | Split register list for renaming | Sree Harsha Kosuru, Eric Dixon, Erik Swanson, Patrick Michael Lowry | 2025-02-18 |
| 12223324 | Methods and apparatus for providing mask register optimization for vector operations | Eric Dixon, Theodore Carlson, Erik Swanson | 2025-02-11 |
| 12204935 | Thread forward progress and/or quality of service | Erik Swanson, Eric Dixon | 2025-01-21 |
| 12118411 | Distributed scheduler providing execution pipe balance | Sneha V. Desai, Erik Swanson, Anilkumar Ranganagoudra | 2024-10-15 |
| 11960897 | Apparatus and methods employing a shared read post register file | Erik Swanson, Eric Dixon, Todd Baumgartner | 2024-04-16 |
| 11907070 | Methods and apparatus for managing register free lists | Eric Busta, Michael L. Golden, Sean M. O′Mullan, James A. Wingfield, Keith Kasprak +1 more | 2024-02-20 |
| 11847463 | Masked multi-lane instruction memory fault handling using fast and slow execution paths | Kai Troester, Scott Thomas Bingham, John M. King, Erik Swanson, Robert Weidner | 2023-12-19 |
| 11842200 | Multi-modal gather operation | John M. King, Magiting M. Talisayon | 2023-12-12 |
| 11709681 | Differential pipeline delays in a coprocessor | Jay Fleischman, Michael Sedmak, Erik Swanson, Sneha V. Desai | 2023-07-25 |
| 11573801 | Method and apparatus for executing vector instructions with merging behavior | Eric Dixon, Erik Swanson, Theodore Carlson, Ruchir Dalal | 2023-02-07 |
| 11567554 | Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics | Jay Fleischman, Michael Sedmak, Erik Swanson, Sneha V. Desai | 2023-01-31 |
| 11544065 | Bit width reconfiguration using a shadow-latch configured register file | Arun A. Nair, Todd Baumgartner, Erik Swanson | 2023-01-03 |
| 11451241 | Setting values of portions of registers based on bit values | Erik Swanson, Sneha V. Desai | 2022-09-20 |
| 11281466 | Register renaming after a non-pickable scheduler queue | Arun A. Nair, Erik Swanson, Sneha V. Desai, Donglin Ji | 2022-03-22 |
| 10776123 | Faster sparse flush recovery by creating groups that are marked based on an instruction type | Erik Swanson, Sneha V. Desai | 2020-09-15 |
| 9959122 | Single cycle instruction pipeline scheduling | Jay Fleischman, Kevin A. Hurd, Mark Gibson, Kelvin D. Goveas, Brian M. Lay | 2018-05-01 |
| 9910638 | Computer-based square root and division operations | Hanbing Liu, John Kelley, Erik Swanson, Jay Fleischman | 2018-03-06 |
| 9575763 | Accelerated reversal of speculative state changes and resource recovery | Jay Fleischman | 2017-02-21 |
| 8819397 | Processor with increased efficiency via control word prediction | Jay Fleischman, Debjit Das Sarma, Emil Talpes, Krishnan V. Ramani, Chun-En Liu | 2014-08-26 |
| 8769247 | Processor with increased efficiency via early instruction completion | Kevin A. Hurd, Jay Fleischman | 2014-07-01 |
| 8671288 | Processor with power control via instruction issuance | Jay Fleischman, Kevin A. Hurd | 2014-03-11 |
| 7206916 | Partial address compares stored in translation lookaside buffer | Harry Ray Fair, III, David R. Akeson | 2007-04-17 |