Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405652 | System and method for controlling power consumption in processor using interconnected event counters and weighted sum accumulators | Richard Martin Born, Gokul Subramani Ramalingam Lakshmi Devi, Larry D. Hewitt | 2025-09-02 |
| 12056522 | Hierarchical asymmetric core attribute detection | Paul Blinzer, Magiting M. Talisayon, Srikanth Masanam, Ripal Butani, Upasanah Swaminathan | 2024-08-06 |
| 11907070 | Methods and apparatus for managing register free lists | Eric Busta, Sean M. O′Mullan, James A. Wingfield, Keith Kasprak, Russell Schreiber +1 more | 2024-02-20 |
| 11853111 | System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction | Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Xiuting Kaleen C. Man +2 more | 2023-12-26 |
| 11704248 | Retaining cache entries of a processor core during a powered-down state | William L. Walker, Marius Evers | 2023-07-18 |
| 11460879 | System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction | Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Xiuting Kaleen C. Man +2 more | 2022-10-04 |
| 10956332 | Retaining cache entries of a processor core during a powered-down state | William L. Walker, Marius Evers | 2021-03-23 |
| 9575553 | Replica path timing adjustment and normalization for adaptive voltage and frequency scaling | Seng Oon Toh, Edward J. McLellan, Stephen V. Kosonocky, Samuel D. Naffziger | 2017-02-21 |
| 7472224 | Reconfigurable processing node including first and second processor cores | Richard E. Klass | 2008-12-30 |
| 7257678 | Dynamic reconfiguration of cache memory | Richard E. Klass | 2007-08-14 |
| 6278308 | Low-power flip-flop circuit employing an asymmetric differential stage | Hamid Partovi, John Yong | 2001-08-21 |