Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405652 | System and method for controlling power consumption in processor using interconnected event counters and weighted sum accumulators | Gokul Subramani Ramalingam Lakshmi Devi, Michael L. Golden, Larry D. Hewitt | 2025-09-02 |
| 12176064 | Apparatus and methods employing asynchronous FIFO buffer with read prediction | David M. Dahle | 2024-12-24 |
| 11967960 | Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications | David M. Dahle, Deepesh John | 2024-04-23 |
| 11853111 | System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction | Amitabh Mehra, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden, Xiuting Kaleen C. Man +2 more | 2023-12-26 |
| 11835998 | System and method for enabling clock stretching during overclocking in response to voltage droop | Amitabh Mehra, Jerry Anton Ahrens, Anil Harwani, Dirk J. Robinson, William Robert Alverson +1 more | 2023-12-05 |
| 11610879 | Power on die discovery in 3D stacked die architectures with varying number of stacked die | Russell Schreiber, Carl Dietz, William A. Halliday | 2023-03-21 |
| 11579650 | Method and apparatus for synchronizing the time stamp counter | Amitabh Mehra, David M. Dahle | 2023-02-14 |
| 11573593 | Level-based droop detection | Stephen V. Kosonocky, Miguel Rodriguez | 2023-02-07 |
| 11460879 | System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction | Amitabh Mehra, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden, Xiuting Kaleen C. Man +2 more | 2022-10-04 |
| 11281280 | Reducing chiplet wakeup latency | Benjamin Tsien, Michael J. Tresidder, Ivan Yanfeng Wang, Kevin M. Lepak, Ann Ling +3 more | 2022-03-22 |
| 10656696 | Reducing chiplet wakeup latency | Benjamin Tsien, Michael J. Tresidder, Ivan Yanfeng Wang, Kevin M. Lepak, Ann Ling +3 more | 2020-05-19 |
| 10642336 | Clock adjustment for voltage droop | Steven J. Kommrusch, Amitabh Mehra, Bobby D. Young | 2020-05-05 |
| 10592442 | Asynchronous buffer with pointer offsets | David M. Dahle, Steven J. Kommrusch | 2020-03-17 |
| 10366027 | I/O writes with cache steering | Eric Christopher Morton, Elizabeth M. Cooper, William L. Walker, Douglas Benson Hunt, Richard H. Lee +3 more | 2019-07-30 |
| 10339063 | Scheduling independent and dependent operations for processing | Paul James Moyer | 2019-07-02 |
| 10168731 | Managing frequency changes of clock signals across different clock domains | Steven J. Kommrusch, Amitabh Mehra | 2019-01-01 |
| 9916243 | Method and apparatus for performing a bus lock and translation lookaside buffer invalidation | William L. Walker, Paul James Moyer, Eric Christopher Morton, David S. Christie, Marius Evers +1 more | 2018-03-13 |
| 7788560 | Interleaver with linear feedback shift register | Cenk Argon, Gregory L. Silvus, Thomas V. Souvignier, Peter Igorevich Vasiliev | 2010-08-31 |
| 7395461 | Low complexity pseudo-random interleaver | Cenk Argon, Gregory L. Silvus, Thomas V. Souvignier, Peter Igorevich Vasiliev | 2008-07-01 |
| 6631484 | System for packet communication where received packet is stored either in a FIFO or in buffer storage based on size of received packet | — | 2003-10-07 |
| 6617893 | Digital variable clock divider | Jackson L. Ellis | 2003-09-09 |
| 6247040 | Method and structure for automated switching between multiple contexts in a storage subsystem target device | Jackson L. Ellis, David Noeldner | 2001-06-12 |
| 6148326 | Method and structure for independent disk and host transfer in a storage subsystem target device | Jackson L. Ellis, David Noeldner | 2000-11-14 |
| 6131108 | Apparatus, and associated method, for generating multi-bit length sequences | Timothy D. Thompson | 2000-10-10 |
| 6115771 | Method and system for converting computer peripheral equipment to SCSI-compliant devices | — | 2000-09-05 |