Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
DH

Douglas Benson Hunt — 26 Patents

AMD: 13 patents #928 of 9,280Top 10%
HP: 11 patents #1,706 of 7,018Top 25%
Fort Collins, CO: #143 of 3,421 inventorsTop 5%
Colorado: #1,349 of 40,980 inventorsTop 4%
Overall (All Time): #150,017 of 4,157,543Top 4%
26 Patents All Time
Douglas Benson Hunt has been granted 26 US patents while listed as an inventor at AMD. The first was granted in 1991 and the most recent in July 2024. Douglas Benson Hunt ranks #150,017 of 4,157,543 US inventors in our database (top 3.6%). Patent records list Douglas Benson Hunt in Fort Collins, CO, US.

Patents per Year

Patents granted per year, 1991 to 2024Bar chart with a peak of 4 patents in 1999.peak 41991: 1 patents19911992: 1 patents1998: 3 patents19981999: 4 patents2000: 1 patents20002001: 1 patents2002: 1 patents20022014: 2 patents2016: 1 patents20162019: 2 patents2020: 2 patents20202021: 3 patents2022: 2 patents20222023: 1 patents2024: 1 patents2024

Issued Patents All Time

Showing 1–25 of 26 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12032965 Throttling while managing upstream resources Paul James Moyer, Kai Troester 2024-07-09 $258,431,000
11669457 Quality of service dirty line tracking Paul James Moyer 2023-06-06
11429647 Domain specific predictive model for entity assessment and valuation 2022-08-30
11294710 Thread switch for accesses to slow memory 2022-04-05 $280,939,000
11169812 Throttling while managing upstream resources Paul James Moyer, Kai Troester 2021-11-09 $495,890,000
11106594 Quality of service dirty line tracking Paul James Moyer 2021-08-31 $371,128,000
10938559 Security key identifier remapping 2021-03-02 $135,206,000
10700954 Scheduling memory bandwidth based on quality of service floorbackground Jay Fleischman 2020-06-30 $39,055,000
10613983 Prefetcher based speculative dynamic random-access memory read request technique Tanuj Kumar Agarwal, Anasua Bhowmik 2020-04-07 $173,261,000
10489218 Suppression of speculative accesses to shared memory locations at a processor William E. Jones 2019-11-26 $74,571,000
10366027 I/O writes with cache steering Eric Christopher Morton, Elizabeth M. Cooper, William L. Walker, Richard Martin Born, Richard H. Lee +3 more 2019-07-30 $35,149,000
9465748 Instruction fetch translation lookaside buffer management to support host and guest O/S translations Prasanta K. Bhowmik 2016-10-11 $4,519,000
8843726 Cache for storing multiple forms of information and a method for controlling a cache storing multiple forms of information 2014-09-23 $5,345,000
8832381 Cache and a method for replacing entries in the cache 2014-09-09 $2,134,000
6353882 Reducing branch prediction interference of opposite well behaved branches sharing history entry by static prediction correctness based updating 2002-03-05 $54,686,000
6308261 Computer system having an instruction for probing memory latency Dale Morris 2001-10-23 $19,288,000
6151672 Methods and apparatus for reducing interference in a branch history table of a microprocessor 2000-11-21 $32,990,000
5956477 Method for processing information in a microprocessor to facilitate debug and performance monitoring Gregory L. Ranson, Gregg B. Lesartre, Russell C. Brockmann, Steven T. Mangelsdorf 1999-09-21 $59,787,000
5893091 Multicasting with key words Mauro Calvi, Carlen Brett Bennett, Robert L. Hines, Jr., James C. Peterson 1999-04-06
5887003 Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results Gregory L. Ranson, Russell C. Brockmann 1999-03-23 $39,742,000
5867644 System and method for on-chip debug support and performance monitoring in a microprocessor Gregory L. Ranson, John W. Bockhaus, Gregg B. Lesartre, Russell C. Brockmann, Robert E. Naas +4 more 1999-02-02 $54,782,000
5781923 Adding a field to the cache tag in a computer system to indicate byte ordering 1998-07-14 $29,752,000
5761490 Changing the meaning of a pre-decode bit in a cache memory depending on branch prediction mode 1998-06-02 $20,710,000
5740391 Preventing premature early exception signaling with special instruction encoding 1998-04-14 $28,534,000
5155832 Method to increase performance in a multi-level cache system by the use of forced cache misses 1992-10-13 $10,655,000