Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204911 | Retire queue compression | Matthew T. Sobel, Joshua James Lindner, Neil N. Marketkar, Emil Talpes, Ashok Tirupathy Venkatachar | 2025-01-21 |
| 12032965 | Throttling while managing upstream resources | Paul James Moyer, Douglas Benson Hunt | 2024-07-09 |
| 11847463 | Masked multi-lane instruction memory fault handling using fast and slow execution paths | Scott Thomas Bingham, John M. King, Michael Estlick, Erik Swanson, Robert Weidner | 2023-12-19 |
| 11467838 | Fastpath microcode sequencer | Magiting M. Talisayon, Hongwen Gao, Benjamin Floering, Emil Talpes | 2022-10-11 |
| 11294724 | Shared resource allocation in a multi-threaded microprocessor | Neil N. Marketkar, Matthew T. Sobel, Srinivas Keshav | 2022-04-05 |
| 11169812 | Throttling while managing upstream resources | Paul James Moyer, Douglas Benson Hunt | 2021-11-09 |
| 11144324 | Retire queue compression | Matthew T. Sobel, Joshua James Lindner, Neil N. Marketkar, Emil Talpes, Ashok Tirupathy Venkatachar | 2021-10-12 |
| 11144353 | Soft watermarking in thread shared resources implemented through thread mediation | — | 2021-10-12 |
| 11048506 | Tracking stores and loads by bypassing load store units | Krishnan V. Ramani, Frank C. Galloway, David N. Suggs, Michael Achenbach, Betty A. McDaniel +1 more | 2021-06-29 |
| 11023241 | Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines | Andrej Kocev, Jay Fleischman, Johnny Chung Leung Chu, Tim J. Wilkens, Neil N. Marketkar +1 more | 2021-06-01 |
| 10331357 | Tracking stores and loads by bypassing load store units | Betty A. McDaniel, Michael Achenbach, David N. Suggs, Frank C. Galloway, Krishnan V. Ramani | 2019-06-25 |
| 9367310 | Stack access tracking using dedicated table | Luke Yen | 2016-06-14 |
| 9292292 | Stack access tracking | Luke Yen | 2016-03-22 |
| 8392757 | Method and apparatus for processing load instructions in a microprocessor having an enhanced instruction decoder and an enhanced load store unit | Krishnan V. Ramani, Mike Butler | 2013-03-05 |