| 12333309 |
Differential pipeline delays in a coprocessor |
Michael Estlick, Michael Sedmak, Erik Swanson, Sneha V. Desai |
2025-06-17 |
|
| 12299445 |
Register based SIMD lookup table operations |
Gabriel H. Loh, Yasuko Eckert, Bradford M. Beckmann, Michael Estlick |
2025-05-13 |
|
| 12282428 |
Selective speculative prefetch requests for a last-level cache |
Tarun Nakra, Akhil Arunkumar, Paul James Moyer |
2025-04-22 |
|
| 12204454 |
System probe aware last level cache insertion bypassing |
Paul James Moyer |
2025-01-21 |
|
| 12153926 |
Processor-guided execution of offloaded instructions using fixed function operations |
John Kalamatianos, Michael T. Clark, Marius Evers, William L. Walker, Paul James Moyer +1 more |
2024-11-26 |
$172,029,000 |
| 11868777 |
Processor-guided execution of offloaded instructions using fixed function operations |
John Kalamatianos, Michael T. Clark, Marius Evers, William L. Walker, Paul James Moyer +1 more |
2024-01-09 |
$241,234,000 |
| 11847062 |
Re-fetching data for L3 cache data evictions into a last-level cache |
Tarun Nakra, Gautam Tarasingh Hazari, Akhil Arunkumar, William L. Walker, Gabriel H. Loh +2 more |
2023-12-19 |
$321,032,000 |
| 11709681 |
Differential pipeline delays in a coprocessor |
Michael Estlick, Michael Sedmak, Erik Swanson, Sneha V. Desai |
2023-07-25 |
$204,977,000 |
| 11567554 |
Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics |
Michael Estlick, Michael Sedmak, Erik Swanson, Sneha V. Desai |
2023-01-31 |
$299,487,000 |
| 11550728 |
System and method for page table caching memory |
Derrick Allen Aguren, Eric Van Tassell, Gabriel H. Loh |
2023-01-10 |
$192,077,000 |
| 11163688 |
System probe aware last level cache insertion bypassing |
Paul James Moyer |
2021-11-02 |
$465,528,000 |
| 11023241 |
Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines |
Andrej Kocev, Kai Troester, Johnny Chung Leung Chu, Tim J. Wilkens, Neil N. Marketkar +1 more |
2021-06-01 |
$332,544,000 |
| 10700954 |
Scheduling memory bandwidth based on quality of service floorbackground |
Douglas Benson Hunt |
2020-06-30 |
$39,055,000 |
| 10223162 |
Mechanism for resource utilization metering in a computer system |
Michael T. Clark, Thaddeus Fortenberry, Maurice B. Steinman |
2019-03-05 |
$23,702,000 |
| 9959122 |
Single cycle instruction pipeline scheduling |
Michael Estlick, Kevin A. Hurd, Mark Gibson, Kelvin D. Goveas, Brian M. Lay |
2018-05-01 |
$7,542,000 |
| 9910638 |
Computer-based square root and division operations |
Hanbing Liu, John Kelley, Michael Estlick, Erik Swanson |
2018-03-06 |
$9,001,000 |
| 9575763 |
Accelerated reversal of speculative state changes and resource recovery |
Michael Estlick |
2017-02-21 |
$8,671,000 |
| 9268575 |
Flush operations in a processor |
Emil Talpes, Debjit Dassarma |
2016-02-23 |
$655,000 |
| 8868633 |
Method and circuitry for square root determination |
Carl E. Lemonds, David M. Russinoff |
2014-10-21 |
$1,689,000 |
| 8819397 |
Processor with increased efficiency via control word prediction |
Michael Estlick, Debjit Das Sarma, Emil Talpes, Krishnan V. Ramani, Chun-En Liu |
2014-08-26 |
$1,803,000 |
| 8769247 |
Processor with increased efficiency via early instruction completion |
Michael Estlick, Kevin A. Hurd |
2014-07-01 |
$4,472,000 |
| 8671288 |
Processor with power control via instruction issuance |
Michael Estlick, Kevin A. Hurd |
2014-03-11 |
$3,598,000 |
| 6550023 |
On-the-fly memory testing and automatic generation of bitmaps |
Jeffery C Brauch |
2003-04-15 |
$12,116,000 |
| 6374370 |
Method and system for flexible control of BIST registers based upon on-chip events |
John W. Bockhaus |
2002-04-16 |
$16,162,000 |
| 6321320 |
Flexible and programmable BIST engine for on-chip memory array testing and characterization |
Jeffery C Brauch, J. Michael Hill |
2001-11-20 |
$21,563,000 |
